Photoresist Mask Etching for Semiconductor Alignment Mark Visibility

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Solution Overview

Problem

Existing semiconductor fabrication processes face visibility issues due to overlay alignment marks having similar heights as the structures formed during etching, limiting their effectiveness in alignment during lithography and patterning.

Innovation Solution

A method is introduced where a photoresist mask is used to selectively etch a target region, forming structures with varying heights, allowing overlay alignment marks to be shorter than the structures in active regions, thereby improving visibility and alignment precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If overlay alignment marks are exposed by the etching process to form structures, then the etching process can remove material to form polysilicon gate structures or inter layer dielectric structures, but the overlay alignment marks and structures have similar heights which leads to overlay alignment mark visibility issues

Engineering Contradiction:
Improvealignment mark visibilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating different height characteristics in different regions of the semiconductor structure. Specifically, the overlay alignment marks are formed with a first height while the surrounding structures (polysilicon gate structures or inter layer dielectric structures) are formed with a second height that is greater than the first height. This local differentiation in height provides vertical separation that improves visibility of the alignment marks without compromising the functional structures.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent resolves the visibility issue by transitioning from a two-dimensional planar distinction to a three-dimensional vertical distinction. Instead of relying solely on lateral positioning or material composition differences, the invention introduces height as an additional dimension for differentiation. The overlay alignment marks are intentionally formed shorter than the adjacent structures, creating a vertical profile difference that enhances detectability while maintaining precise alignment functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If overlay alignment marks are formed with the same height as structures, then the etching process is simple and uniform, but the visibility of overlay alignment marks is limited

Engineering Contradiction:
Improveetching process simplicityVSAvoidalignment mark detection
Core Design Contradiction:
Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements local quality by applying different etching conditions to different regions of the substrate. The overlay alignment mark regions are etched to a first depth, while the surrounding active regions are etched to a greater second depth. This localized differentiation in etching depth creates the desired height variation that improves detection capability while maintaining manufacturing feasibility through region-specific process parameters.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances overlay alignment mark visibility and precision during semiconductor fabrication by creating structures with distinct height differences, facilitating better alignment and patterning processes.

Implementation Method 1

A first etch is performed through the open region to remove a portion of the target region

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10957653B2Methods for manufacturing semiconductor arrangements using photoresist masks
Publication Date: 2021.03.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10957653B2 patent drawing
  • US10957653B2 patent drawing
  • US10957653B2 patent drawing

AI summary

Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.