Photosensitive Array Integrated Backplane Stamping Fabrication
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Solution Overview
Problem
Existing photosensitive devices, such as CCD and CMOS sensors, require a separate fabrication of the transistor backplane, which can lead to increased complexity and risk of damage to heat-sensitive materials due to high-temperature deposition processes, limiting their sensitivity and performance.
Innovation Solution
The integration of a transistor backplane within the photosensitive array is achieved through a stamping process using elastomeric stamps combined with full-surface deposition of layers on planar or non-planar substrates, allowing for lower-temperature bonding and improved alignment of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a separate transistor backplane is fabricated and then assembled to the photosensitive array, then the device complexity is reduced in terms of integration, but the manufacturing precision deteriorates due to alignment issues and the risk of damage to heat-sensitive materials during high-temperature deposition processes
Solution Approach 1:
The patent merges the transistor backplane fabrication with the photosensitive array fabrication by depositing transistor layers directly over the photosensitive pixels on the same substrate. This integration eliminates the need for separate backplane fabrication and assembly, thereby improving alignment precision and preventing damage to heat-sensitive materials that would occur during separate high-temperature processing steps.
2Reliability
If high-temperature deposition processes are used to fabricate the transistor backplane, then the transistor performance is improved, but the photosensitive materials deteriorate due to heat damage
Solution Approach 1:
The patent changes the deposition temperature parameter by using low-temperature deposition techniques (such as atomic layer deposition or chemical vapor deposition at reduced temperatures) to fabricate the transistor backplane. This allows the transistor structures to be formed without exposing the photosensitive materials to damaging high temperatures, thereby preserving photosensitive material integrity while still achieving functional transistor performance.
Data Source
AI summary
A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.