Polymer layer in semiconductor device and method of manufacture

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and small footprint packaging due to limitations in current packaging techniques, particularly in forming efficient dielectric layers for semiconductor devices, which affect the performance and reliability of packaged components.

Innovation Solution

The use of a polyimide material to form dielectric layers with specific polymer precursors, cross-linkers, and photosensitizers, allowing for the creation of dielectric layers with reduced dissipation factor and improved mechanical properties, such as lower coefficient of thermal expansion and higher adhesion, which enhances the integration density and reliability of semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and component density are limited

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging technique complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements Package-on-Package (PoP) technology where a top semiconductor package is stacked on top of a bottom semiconductor package, creating a nested vertical arrangement that dramatically increases integration density without increasing PCB footprint area

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The invention transitions from traditional planar packaging to three-dimensional vertical stacking, utilizing the vertical dimension to accommodate multiple semiconductor packages and enhance component density while maintaining a small PCB footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If dielectric layers with traditional materials are used, then manufacturing process is simpler, but dissipation factor is higher causing increased insertion loss

Engineering Contradiction:
Improveinsertion lossVSAvoiddielectric layer formulation complexity
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The patent employs a composite dielectric layer comprising polyimide material with specific additives including glass flakes, metal particles, or ceramic fillers embedded within the polymer matrix, creating a multi-phase composite that optimizes both electrical performance and mechanical properties

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The invention modifies the dielectric layer composition by controlling the weight percentages of polyimide (5-50%), glass flakes (30-60%), and metal particles (5-20%), and by adjusting the coefficient of thermal expansion to match underlying substrates, thereby reducing insertion loss while maintaining manufacturability

Inventive Principle:
Principle #35Parameter changes

3Strength

If standard polymer materials are used for dielectric layers, then ease of manufacture is maintained, but adhesion and mechanical strength are insufficient

Engineering Contradiction:
Improvedielectric layer adhesionVSAvoidmaterial processing complexity
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The patent enhances the dielectric layer by incorporating reinforcing fillers such as glass flakes and metal particles within the polyimide matrix, creating a composite material that simultaneously improves adhesion strength, mechanical rigidity, and thermal stability

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The invention adjusts the polymer precursor molecular weight, cross-linker concentration, and curing temperature parameters to optimize the dielectric layer's adhesion properties and mechanical strength while maintaining ease of application and processing

Inventive Principle:
Principle #35Parameter changes

4Quantity of substance

If high integration density is achieved through stacking, then component density improves, but stress on solder joints increases causing reliability issues

Engineering Contradiction:
Improvecomponent densityVSAvoidsolder joint reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent modifies the dielectric layer's coefficient of thermal expansion to match that of the underlying substrate and solder joints, reducing thermal mismatch stress during temperature cycling and improving the reliability of vertical interconnects in stacked packages

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention specifically addresses thermal expansion mismatch by formulating the dielectric layer with fillers that adjust its thermal expansion characteristics, thereby minimizing stress on solder joints and conductive interconnects during thermal cycling in high-density stacked configurations

Inventive Principle:
Principle #37Thermal expansion

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of semiconductor packages with improved integration density, reduced device insertion loss, and increased reliability by lowering stress on solder joints and reducing broken conductive lines, while also allowing for higher resolution and throughput in manufacturing.

Implementation Method 1

The polymer precursor includes a polymer backbone with pendant vinyl groups that cross-link upon exposure to light

Methodology Applied
Scientific EffectPhotopolymerization: Photopolymerisation

Implementation Method 2

curing the polymer material at a temperature in a range of 200° C. to 300° C.

Methodology Applied
Scientific EffectThermal curing: Heat Treatment

Data Source

PatentUS11868047B2Polymer layer in semiconductor device and method of manufacture
Publication Date: 2024.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11868047B2 patent drawing
  • US11868047B2 patent drawing
  • US11868047B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.