Photovoltaic Cell Bus Layout for Front Collector Voltage Drop
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Solution Overview
Problem
Existing photovoltaic cells in portable objects suffer from significant voltage drops and power losses due to the higher resistance of the front collector, which is typically made of a transparent conductive oxide, compared to the rear collector, leading to inefficient energy conversion.
Innovation Solution
The photovoltaic cell design incorporates asymmetrical peripheral buses, with the front collector bus being significantly longer than the rear collector bus, and the front collector bus is connected to two positive terminals via a flexible connector, reducing the voltage drop and power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If symmetrical peripheral buses are used in photovoltaic cell design, then manufacturing simplicity is maintained, but voltage drop and power loss increase due to higher resistance in the front collector
Solution Approach 1:
The patent applies asymmetry by designing the front collector bus to be significantly longer than the rear collector bus. The front collector bus extends along the entire circumference of the circular photovoltaic cell, while the rear collector bus is shorter and positioned to minimize resistance. This asymmetric configuration reduces voltage drop in the high-resistance front collector without unnecessarily complicating the overall bus arrangement.
Solution Approach 2:
The patent implements local quality by optimizing the bus configuration specifically where it is most needed - the front collector. Since the front collector has much higher resistance than the rear collector, the design provides enhanced bus coverage and connectivity in this specific region while maintaining simpler configuration in the low-resistance rear collector area.
2Loss of energy
If the front collector bus is made longer to reduce voltage drop, then energy loss decreases, but the device complexity increases
Solution Approach 1:
The patent resolves this contradiction by creating an asymmetric bus design where the front collector bus is deliberately made longer than the rear collector bus. This asymmetric configuration targets the specific problem area (high-resistance front collector) with enhanced bus coverage, reducing power loss without requiring proportional increases in overall bus complexity.
Solution Approach 2:
The patent changes the geometric parameters of the bus configuration, specifically the length and positioning of the front collector bus relative to the rear collector bus. By adjusting these parameters asymmetrically, the design optimizes electrical performance (reducing voltage drop) while controlling the complexity of the overall bus arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively limits the voltage drop across the front collector to less than 100 mV, resulting in a gain of almost 50 mV compared to symmetrical designs, enhancing the efficiency of the photovoltaic cell.
Implementation Method 1
a p-i-n type sequence (p-doped, intrinsic i, n-doped) of amorphous silicon (a-Si) thin layers, referred to as an absorber, which converts the absorbed light radiation into positive electric charge carriers (holes) and negative electric charge carriers (electrons)
Data Source
AI summary
A photovoltaic cell (1) including a first front collector layer (4), an amorphous silicon layer (6) on the first layer (4) and a second conductive layer (8) on the amorphous silicon layer (6). Electrical connection of the second conductive layer (8) to the first layer (4) is made through the amorphous silicon layer (6) at the periphery of the photovoltaic cell, the electrically conductive layer (8) comprising a positive peripheral bus (8′), which is connected to the TCO first layer (4) and to at least one positive connection terminal at one end of the positive peripheral bus, and a negative peripheral bus, which is connected to a negative connection terminal, and the positive and negative peripheral buses being asymmetrical relative to one another, with the positive peripheral bus being longer than the negative peripheral bus.