Hardware Payload Header Suppression Engine for DOCSIS Networks

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Solution Overview

Problem

Cable modem systems face significant processing overhead due to software-based payload header verification and suppression, limiting the number of cable modems that can be supported by a single cable modem termination system.

Innovation Solution

Implementing a hardware-based payload header suppression engine that passes Ethernet packets between a DOCSIS direct memory access controller and a DOCSIS header creator, using separate FIFOs for PHS rule verification and suppression, and including a payload header suppression index for packet transmission and expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If software is used to perform payload header verification and suppression, then the system can maintain flexibility and ease of implementation, but processing overhead increases significantly

Engineering Contradiction:

Improveease of implementationVSAvoidprocessing overhead

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent replaces software-based payload header verification and suppression with dedicated hardware circuits. The verification circuit compares payload headers against stored rules in parallel, and the suppression circuit selectively removes matching headers at the hardware level, eliminating the processing overhead inherent in software implementations while maintaining the functional flexibility of rule-based suppression.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If software-based processing is used, then device complexity remains manageable, but the number of supported cable modems per termination system is reduced

Engineering Contradiction:

Improvedevice complexityVSAvoidnumber of supported cable modems

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent implements hardware circuits for payload header verification and suppression that operate in parallel and independently of the main processing pipeline. This dedicated hardware approach significantly increases processing capacity and throughput, enabling a single cable modem termination system to support many more cable modems compared to software-based implementations, while the modular circuit design keeps overall device complexity manageable.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If payload header suppression is implemented, then data transmission efficiency improves, but verification complexity increases

Engineering Contradiction:

Improvedata transmission efficiencyVSAvoidverification complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the payload header processing into separate functional circuits: a verification circuit that compares headers against rules, a suppression circuit that removes matching headers, and an expansion circuit that restores them at the receiver. This segmentation allows each circuit to perform its specific function efficiently, reducing overall verification complexity while maintaining high data transmission efficiency through selective suppression.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate storage structures (FIFO buffers and rule tables) that hold payload headers and suppression rules during processing. These intermediaries decouple the verification, suppression, and expansion operations, allowing them to proceed independently and efficiently without requiring complex coordination, thus reducing verification complexity while improving data transmission efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7599369B2Apparatus and methods for hardware payload header suppression, expansion, and verification in a DOCSIS network

Publication Date: 2009.10.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, one or more bits are suppressed in the payload header and a the payload header suppressed and a payload header suppression index is added to the suppressed packet payload header. Following transmission, the suppression indexed is used to identify the bits to be reinserted into the suppressed payload header.