Serial Differential Link Blocking State for PHY Lane Tasks
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Solution Overview
Problem
As computing systems evolve with increased processing power and complexity, existing interconnect architectures struggle to meet the demands for high-performance communication between components, particularly in high-performance computing environments like servers, where the communication between multiple sockets and devices becomes critical, and existing interconnects face challenges in handling the growing bandwidth requirements.
Innovation Solution
A new High Performance Interconnect (HPI) architecture is introduced, featuring a layered protocol stack with a coherent, link-based design that includes a transaction layer, link layer, and physical layer, supporting credit-based flow control, virtual channels, and a coherence protocol to ensure efficient data transfer and maintain data consistency across multiple processors and devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing interconnect architectures are used to handle increased bandwidth requirements, then communication between sockets and devices becomes more critical, but the interconnect architecture becomes insufficient to meet the demands for high-performance communication
Solution Approach 1:
The interconnect architecture is segmented into multiple virtual channels (VC0, VC1, VC2, VC3) that operate independently. Each virtual channel can transmit different types of transactions simultaneously, dividing the bandwidth into separate pathways to reduce contention and improve overall communication performance.
Solution Approach 2:
The patent introduces virtual channels as an additional dimension beyond traditional physical lanes. By multiplexing multiple virtual channels across the physical interconnect, the system achieves higher bandwidth without proportionally increasing physical complexity, effectively adding a virtual dimension to the communication pathway.
2Productivity
If multiple virtual channels are implemented to increase bandwidth, then communication efficiency improves, but the complexity of managing coherence and data consistency increases
Solution Approach 1:
The coherence management mechanism uses feedback signals (Snoop Enable, Snoop Response, Invalidate) to maintain data consistency across multiple virtual channels. When a cache line is accessed or modified, feedback signals coordinate the appropriate invalidation or update operations across other channels, ensuring coherence without requiring complex centralized control.
Solution Approach 2:
Each virtual channel maintains its own coherence state independently, with local coherence tracking at each channel level. This allows individual channels to manage their coherence requirements locally rather than requiring global coordination, reducing the overall complexity of coherence management across the multi-channel system.
3Productivity
If credit-based flow control is implemented to manage data transfer, then data transfer efficiency improves, but the complexity of flow control management increases
Solution Approach 1:
Credit-based flow control operates on the principle of preliminary action by pre-establishing credit counters at both transmitter and receiver ends. These counters track available buffer space before data transmission occurs, allowing the system to prepare flow control state in advance and avoid complex real-time negotiation during active data transfer.
Solution Approach 2:
The flow control mechanism is self-managing through automated credit counter operations. When a transmitter sends data, it automatically decrements its credit counter and increments the receiver's credit counter. The receiver similarly manages its own buffer state, eliminating the need for external flow control management and reducing system complexity.
Data Source
AI summary
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.