PHY Chip Integrated PoE Power Control and Device Analysis
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Solution Overview
Problem
Conventional Power-over-Ethernet (PoE) systems are inefficient due to the need for a separate power sourcing equipment (PSE) chip and host CPU involvement in power analysis and control, which increases costs and processing time, and require additional communication interfaces.
Innovation Solution
A PD analysis and power control system integrated within the PHY chip, utilizing existing logic and algorithms to analyze device characteristics through signal pulses, eliminating the need for a PSE controller chip by directly managing power supply and status indication within the PHY chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a separate PSE chip and host CPU are used for power analysis and control, then power management functionality is achieved, but system complexity and cost increase
Solution Approach 1:
The patent integrates the PSE chip functionality directly into the PHY chip, merging previously separate power management and physical layer functions into a single integrated component. This eliminates the need for separate PSE and CPU involvement in power analysis, reducing system complexity while maintaining complete power management functionality through the unified chip architecture.
Solution Approach 2:
The PHY chip is enhanced to perform multiple functions including both physical layer operations and power analysis/control. By making the PHY chip universal and multi-functional, the system eliminates the need for dedicated separate components, thereby reducing overall system complexity without compromising power management capabilities.
2Productivity
If a separate PSE chip is used for power analysis, then power control is achieved, but processing time and power consumption increase
Solution Approach 1:
By merging PSE functionality into the PHY chip, the patent eliminates the need for data transfer between separate chips and CPU, thereby reducing processing time for power analysis and control operations.
Solution Approach 2:
The integrated PHY chip performs power analysis and control operations autonomously without requiring CPU intervention or additional processing steps, enabling self-service operation that reduces both processing time and overall system power consumption.
3Device complexity
If additional communication interfaces are used for power control, then power management is achieved, but system cost and complexity increase
Solution Approach 1:
The patent combines power control functionality with the existing Ethernet communication interface within the PHY chip, eliminating the need for separate communication interfaces. This integration maintains full power control capability while reducing the number of interfaces and overall system complexity.
Solution Approach 2:
The Ethernet interface within the PHY chip is made multi-functional, serving both data communication and power management purposes. This universal interface approach eliminates the need for additional dedicated communication interfaces while preserving complete power control functionality.
Data Source
AI summary
A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.