PHY Clock Master Initialization Timing Control
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Solution Overview
Problem
Existing methods for high-speed communication devices, such as those using the 1000BASE-T standard, fail to establish link-ups without timing adjustment between clock slave and clock master initialization, leading to potential clock errors and frame loss, making them unsuitable for high-speed communication.
Innovation Solution
A communication device where the first physical layer circuit is set as a clock master to transmit a clock signal only after the second physical layer circuit, set as a clock slave, completes its initialization, ensuring synchronization without autonegotiation and automatic cable identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If autonegotiation is used to automatically set communication parameters, then ease of operation is improved, but time for link establishment increases
Solution Approach 1:
The patent stores communication setting information including clock master/slave determination and MDI/MDI-X selection in advance before autonegotiation is disabled. This preliminary storage of configuration data allows the system to skip the time-consuming autonegotiation process while maintaining automatic parameter setting capabilities through pre-configured values.
Solution Approach 2:
The patent extracts and removes the autonegotiation function from the link establishment process. By disabling autonegotiation and using pre-stored communication setting information, the system eliminates the time-consuming negotiation phase while retaining essential automatic configuration through pre-determined settings.
2Reliability
If timing adjustment between clock slave and clock master initialization is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent determines and stores the clock master/slave relationship in advance through autonegotiation before disabling the function. This preliminary determination simplifies the timing control mechanism by pre-establishing which device should initialize first, eliminating the need for complex real-time timing negotiation while ensuring synchronization reliability.
Solution Approach 2:
The system uses pre-stored communication setting information to automatically control initialization timing without requiring complex external timing adjustment mechanisms. Each device refers to its stored configuration to determine when to initialize, enabling self-service timing control that maintains reliability without adding device complexity.
3Productivity
If autonegotiation is disabled to reduce link establishment time, then productivity is improved, but reliability of high-speed communication decreases
Solution Approach 1:
The patent performs autonegotiation in advance to determine communication parameters including clock master/slave assignment and MDI/MDI-X selection, then stores this information for later use. This preliminary action enables rapid link re-establishment without repeated negotiation while maintaining communication stability through pre-determined optimal settings.
Solution Approach 2:
The system creates a copy of the communication setting information determined through initial autonegotiation and stores it for reuse. This copying approach allows the system to maintain reliable communication parameters without repeatedly performing time-consuming autonegotiation, thus improving productivity while preserving communication stability.
Data Source
AI summary
A first PHY (121) transmits and receives signals, at a physical layer, to and from a second PHY (142) in a communication device (101) through a communication cable (601). The first PHY (121) is set as a clock master to transmit, to the second PHY (142), a clock signal defining timing for transmitting and receiving signals. A device controller (151), in response to detection of a set event, completes initialization of the first PHY (121) set as the clock master after completion of initialization of the second PHY (142) set as a clock slave.