PHY Interface Clock Synchronization Without FIFO Buffers
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Solution Overview
Problem
The existing physical layer interface of computing devices faces challenges in clock signal alignment and distribution, leading to increased latency and chip area usage, particularly due to asynchronous clock frequencies between the memory controller and DRAM, which necessitates a significant number of FIFO buffers and power-consuming independent distribution networks for clock and reset signals.
Innovation Solution
The method involves generating a reference clock signal and synchronizing multiple clock signals using phase locked loops and feedback mechanisms to align clock edges, eliminating the need for FIFO buffers and reducing chip area and power consumption by distributing clock and reset signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous clock signals with different frequencies are used to clock the memory controller and PHY, then the memory controller can operate at flexible frequencies, but FIFO buffers are needed to handle the frequency mismatch and alignment uncertainty
Solution Approach 1:
The patent merges the clock generation for the memory controller and PHY into a single synchronized system using a common reference clock. This eliminates the need for separate asynchronous clock sources and the FIFO buffers that would be required to handle frequency mismatches between independent clock domains.
Solution Approach 2:
The patent implements feedback mechanisms through phase alignment detection and adjustment circuits that monitor the relative phase between clock signals and dynamically adjust timing to maintain synchronization. This feedback loop eliminates the need for buffering by continuously maintaining clock alignment.
2Reliability
If independent distribution networks are used for clock and reset signals, then signal integrity can be maintained, but chip area and power consumption increase
Solution Approach 1:
The patent combines the distribution of clock and reset signals into a single integrated distribution network. By coupling the reset signal distribution with the clock signal distribution infrastructure, the patent reduces the total chip area required while maintaining proper signal integrity through coordinated timing control.
3Reliability
If multiple FIFO buffers are used to handle asynchronous clock domains, then data transfer reliability is improved, but latency and chip area increase
Solution Approach 1:
The patent extracts and eliminates the need for FIFO buffers by removing the asynchronous clock domain interface. Through synchronized clock distribution and phase alignment, the patent directly connects the memory controller and PHY clock domains, thereby removing the buffering stage that would introduce latency while maintaining data transfer reliability.
4Productivity
If synchronized clock signals are used throughout the system, then latency and chip area are reduced, but clock alignment and distribution become more challenging
Solution Approach 1:
The patent introduces a reference clock signal as an intermediary that serves as the master synchronization source for both the memory controller and PHY. This intermediary reference clock simplifies the alignment process by providing a common timing基准 that all other clocks derive from, reducing the overall complexity of maintaining synchronization across the system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach synchronizes clock signals across the physical layer and memory controller, reducing latency and chip area usage while minimizing power consumption, thereby enhancing integration efficiency and reducing the complexity of clock signal distribution.
Implementation Method 1
synchronizing multiple clock signals as a function of the reference clock signal using phase locked loops
Data Source
AI summary
A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.