Multi-Chip PHY Deskewing with Lane-Wise Clock Phase Alignment
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Solution Overview
Problem
The alignment of data and clock signals between functional blocks in semiconductor chips often results in misalignment, leading to increased latency during signal transfer, particularly in multi-chip modules with wide communication lanes.
Innovation Solution
Implementing a circuit that synchronizes local clocks with global clocks using a barrel shifter and control logic to adjust phases, combined with a FIFO mode to manage timing margins, achieving synchronous clock-domain crossing with reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional signal alignment methods are used to realign misaligned data and clock signals, then signal alignment is improved, but latency increases significantly
Solution Approach 1:
The patent applies preliminary action by performing deskewing operations during a training phase before actual data transmission begins. The control logic sweeps through possible phase offsets and determines the correct alignment in advance, storing this information for use during normal operation. This allows the system to achieve precise signal alignment without incurring latency during actual data transfer, as the alignment work is completed beforehand.
2Measurement precision
If deskewing operations are performed across all lanes simultaneously, then alignment accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies segmentation by dividing the deskewing process into separate operations for each communication lane. The control logic processes lanes individually, determining and correcting phase offsets for one lane at a time rather than attempting to align all lanes simultaneously. This segmentation reduces the overall processing time while maintaining alignment accuracy, as each lane can be processed independently and in sequence.
Data Source
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AI summary
Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.