PHY Forward Error Correction Using Variable Phits for Low Latency
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Solution Overview
Problem
Existing FEC schemes in high-speed networks and storage systems, such as Gen-Z, face latency issues due to large codeword sizes and complex decoders, which are not optimal for low-latency applications like High Performance Computing and memory-semantic operations.
Innovation Solution
The implementation of low-latency forward error correction techniques using pre-coding, binary BCH encoding, and variable-sized phits with a control bit sanity check to minimize codeword length and correction latency, specifically designed for Gen-Z systems to reduce latency and error correction overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stronger and more sophisticated FEC schemes are introduced to maintain link reliability at higher bandwidths, then error correction capability is improved, but codeword size and decoder complexity increase resulting in high latency
Solution Approach 1:
The data stream is segmented into fixed-size physical units (phits) of 256 bits each, with FEC codewords spanning multiple phits. This segmentation allows the FEC decoder to process data in manageable chunks rather than requiring extremely large codewords, reducing decoder complexity and latency while maintaining error correction capability across the segmented units through cross-phit parity bits.
Solution Approach 2:
The patent changes the FEC coding parameters by using a specific rate-1/2 binary BCH encoding scheme with 256-bit phits, where each data phit generates one parity phit. This parameter configuration achieves optimal balance between error correction strength and latency, processing each 256-bit unit in a fixed number of clock cycles regardless of error pattern complexity.
2Reliability
If larger codeword sizes are used to provide stronger error correction, then error correction capability is improved, but decoder complexity and latency increase
Solution Approach 1:
The FEC scheme segments the data into fixed 256-bit phits, with each data phit paired with one parity phit of the same size. This segmentation transforms the decoder complexity from needing to handle extremely large codewords to processing manageable 256-bit units in a fixed number of clock cycles, significantly reducing device complexity while maintaining strong error correction through the systematic parity distribution across multiple phits.
3Reliability
If traditional FEC schemes with large codeword sizes are used, then link reliability is maintained, but end-to-end switch latency increases
Solution Approach 1:
The patent performs preliminary organization of data into fixed-size 256-bit phits with pre-calculated systematic parity bits before transmission. The receiver performs preliminary syndrome calculation and error pattern identification on these pre-organized units, enabling fixed-time decoding regardless of error severity. This preliminary structuring eliminates variable decoding times that occur in traditional schemes, ensuring predictable low latency for high-speed switching applications.
Data Source
AI summary
Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.