Serial Differential PHY Link Control for Flit Blocking Tasks
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly in servers and mobile devices, as they struggle to scale effectively with the growing complexity of computing components and the need for faster communication between processors and devices.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and a coherence protocol to support cache-coherent systems, enabling efficient data transfer and management across multiple devices and processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used, then device complexity is reduced, but communication performance and bandwidth deteriorate
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links instead of a shared bus. Each link has dedicated bandwidth and can operate independently, eliminating the bandwidth contention inherent in shared multi-drop buses while maintaining manageable complexity through modular link design.
Solution Approach 2:
The architecture transitions from a two-dimensional shared bus structure to a three-dimensional hierarchical topology with multiple levels (L0, L1, L2) and multiple simultaneous communication paths. This dimensional expansion provides parallel communication channels that dramatically increase bandwidth without proportionally increasing complexity.
2Productivity
If processing power and number of devices are increased, then computational capability is improved, but communication requirements and power consumption worsen
Solution Approach 1:
The interconnect supports dynamic link width adjustment where links can operate at different widths (e.g., 128-bit, 64-bit) depending on bandwidth demands. This allows the system to allocate power and bandwidth resources dynamically - using full width for high-performance computing tasks and reduced width for less demanding operations, thereby reducing average power consumption while maintaining peak computational capability.
Solution Approach 2:
The communication infrastructure is divided into multiple independent point-to-point links that can be activated or deactivated based on actual communication needs. This segmentation allows the system to reduce power consumption by keeping fewer links active during low-demand periods while maintaining the capability to scale up when computational tasks require high bandwidth.
3Productivity
If link width is increased, then data transfer bandwidth is improved, but signal integrity and manufacturing precision worsen
Solution Approach 1:
Instead of building a single wide link, the architecture uses multiple narrower point-to-point links that can be aggregated to achieve the required total bandwidth. Each narrow link maintains excellent signal integrity and is easier to manufacture, while the collective bandwidth of multiple links provides the necessary data transfer capacity. This segmentation approach trades a single wide link for multiple manageable narrow links.
Data Source
AI summary
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.