PHY Header Descriptor Array for Low-Latency Packet Retransmission
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Solution Overview
Problem
Existing packet data networks face challenges in minimizing packet error rates (PER) due to short burst noises, particularly in the automotive industry, where traditional error correction mechanisms in the PHY and data link layers lead to high latency and inefficient re-transmission processes.
Innovation Solution
A physical (PHY) layer with a header descriptor array (HDA) that stores and accesses packet header fields, utilizing a write and read interface module to manage header fields, track status signals, and enable parallel processing for ultra-low PER and low latency, incorporating error detection and re-transmission mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial processing methods are used for error correction in data link layer, then packet error rate is reduced, but transmission latency increases
Solution Approach 1:
The patent segments the error correction process by implementing separate functional modules: a header descriptor array (HDA) for parallel header field access, a data packet buffer for parallel packet storage, and a centralized module for coordinating retransmission requests. This segmentation allows multiple packets to be processed simultaneously at different stages, reducing overall latency while maintaining error correction capability.
Solution Approach 2:
The patent performs preliminary actions by pre-storing packet header fields in the HDA and maintaining packet copies in the buffer before error correction is needed. When errors are detected, retransmission can immediately occur using pre-prepared data, eliminating the need for time-consuming sequential retrieval and correction operations.
2Loss of time
If parallel processing is implemented for packet handling, then transmission latency is reduced, but system complexity increases
Solution Approach 1:
The patent merges multiple functions into a centralized module that coordinates the HDA, packet buffer, and retransmission logic. This centralized control structure manages parallel operations without requiring complex distributed synchronization, reducing overall system complexity while enabling parallel processing of multiple packets through shared resources.
3Productivity
If multiple header fields are stored and accessed in parallel, then error correction speed is improved, but memory requirements increase
Solution Approach 1:
The patent extracts only the essential header fields needed for error detection and retransmission control into the HDA, rather than storing complete packet data in parallel. This selective extraction of critical metadata enables fast parallel access for error correction decisions while minimizing memory consumption compared to storing full packet copies for all operations.
Data Source
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AI summary
A method for managing packet header fields in a physical (PHY) layer includes: receiving, by a header descriptor array (HDA) of a PHY layer, a data packet and a status signal of the data packet; writing, by the HDA, a header field for the received data packet; storing, by the HDA, the written header field and the status signal of the data packet in a header field array; and fetching, by the HDA, the header field of the data packet by enabling parallel reading of a plurality of locations of the header field array, enabling transmission and re-transmission of the data packet.