Interconnect Physical Layer Latency Alignment for Fast Link Training
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly as the number of processing devices grows, leading to inefficiencies in communication between sockets and devices.
Innovation Solution
A High Performance Interconnect (HPI) architecture is introduced, featuring a layered protocol stack with a point-to-point link structure, credit-based flow control, and a physical layer optimized for fast data transfer, enabling efficient communication and power management across multiple processors and devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for electrical communications, then device complexity is reduced, but bandwidth and communication performance deteriorate
Solution Approach 1:
The interconnect architecture is segmented into multiple point-to-point links rather than using a single shared bus. Each link connects specific devices directly, enabling parallel data transmission paths and eliminating the bandwidth bottleneck of shared buses while maintaining manageable complexity through modular link design.
Solution Approach 2:
The architecture transitions from a one-dimensional shared bus to a multi-dimensional mesh-like structure with multiple simultaneous communication paths. This dimensional expansion allows concurrent data transfers across different links, dramatically increasing total bandwidth without proportionally increasing complexity.
2Power
If the number of processing devices and sockets increases, then computing power is improved, but communication efficiency and power consumption deteriorate
Solution Approach 1:
The interconnect system dynamically activates or deactivates communication links based on actual data transfer requirements. This dynamic behavior allows the system to maintain high computing power through selective engagement of processing devices while reducing overall power consumption by keeping inactive links in low-power states.
Solution Approach 2:
The architecture extracts and optimizes the communication function from the computing function. By separating data communication paths from processing logic, the system can efficiently route only necessary data between sockets and devices, reducing unnecessary power consumption while maintaining high computing capability.
3Power
If the number of processing devices increases, then computing power is improved, but communication efficiency deteriorates
Solution Approach 1:
The patent introduces intermediary components (such as switches or routers) that mediate communication between processing devices. These intermediaries efficiently route data between sockets and devices, maintaining communication efficiency even as the number of devices increases, thereby supporting higher computing power without sacrificing communication performance.
Solution Approach 2:
The communication infrastructure is segmented into dedicated point-to-point links for each device pair, eliminating shared bus contention. This segmentation ensures that increasing the number of devices does not degrade communication efficiency, as each device has dedicated pathways for data transfer.
4Ease of manufacture
If traditional interconnect architectures are used, then ease of manufacture is maintained, but bandwidth demand cannot be met
Solution Approach 1:
The interconnect is segmented into standardized point-to-point link modules that can be manufactured using conventional processes. Each module uses standard electrical interfaces and packaging, maintaining ease of manufacture while the collective network of modules provides the required high bandwidth capacity.
Data Source
AI summary
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.