Physical Layer Clock Synchronization Bypassing CPU Limits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing IEEE 1588 clock synchronization technologies have limited user capacity and high synchronization costs due to CPU architecture limitations, which are exacerbated in large-scale networking applications like femto/micro stations, leading to insufficient time service capacity and increased costs.

Innovation Solution

A clock synchronization method and apparatus where a physical layer device acquires and transmits synchronization messages, utilizing a CPU to generate initial messages with timestamps, and prioritizing signaling messages to maximize Ethernet bandwidth, thereby bypassing CPU processing limitations and enhancing user capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CPU processes 1588 synchronization messages through software interrupt, then synchronization precision is achieved, but user capacity is limited to dozens of users

Engineering Contradiction:
Improvesynchronization precisionVSAvoiduser capacity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the 1588 message processing function from the CPU by introducing a dedicated physical layer device. The CPU handles high-level control while the physical layer device handles timestamp generation and message processing, allowing parallel operation and significantly increasing user capacity beyond the CPU's software interrupt limitations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a physical layer device as an intermediary between the CPU and the 1588 synchronization process. This intermediary handles the time-critical timestamp generation and message processing, freeing the CPU from software interrupt overhead and enabling support for hundreds or thousands of users while maintaining synchronization precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If specialized high-performance IEEE 1588 synchronization server is used, then user capacity increases to over 1000 users, but synchronization cost increases

Engineering Contradiction:
Improveuser capacityVSAvoidsynchronization cost
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent enables the physical layer device to self-service the timestamp generation and synchronization message processing without requiring expensive specialized servers. By utilizing existing Ethernet bandwidth and hardware capabilities already present in the system, it achieves high user capacity (hundreds to thousands of users) without the additional cost of dedicated synchronization infrastructure.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent makes the physical layer device multi-functional by having it handle both data transmission and synchronization timestamp generation. This universal approach eliminates the need for separate specialized synchronization servers, reducing overall system cost while maintaining the ability to serve hundreds or thousands of users simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If Ethernet bandwidth is fully utilized for synchronization messages, then user capacity increases to hundreds of thousands, but message processing complexity increases

Engineering Contradiction:
Improveuser capacityVSAvoidmessage processing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the complex timestamp generation and message processing logic from the CPU software layer and places it in the physical layer device's hardware. This extraction simplifies the overall system architecture by handling processing complexity at the hardware level where it can operate efficiently in parallel, enabling full Ethernet bandwidth utilization for supporting hundreds of thousands of users.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3163786B1Clock synchronization method and apparatus
Publication Date: 2019.12.04 ZTE CORP
  • EP3163786B1 patent drawingFigure 1~2
  • EP3163786B1 patent drawingFigure 3~5
  • EP3163786B1 patent drawingFigure 6~7

AI summary

The present invention provides a clock synchronization method and a clock synchronization apparatus. Herein the method includes: a physical layer device acquires a synchronization message used for a device to be synchronized to implement clock synchronization; and the physical side device transmits the synchronization message to the device to be synchronized. By means of the abovementioned technical solution provided by the present invention, the problems of small user capacity of the load and high synchronization cost resulted from the clock synchronization method in existing technologies are solved, the insufficient user capacity of the load caused by the limit of the CPU architecture is avoided, and the bandwidth resource of the Ethernet is utilized to the maximum extent.