PHY Line Coding With FEC and Scrambling for Severe Noise

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Solution Overview

Problem

High-speed data networks face challenges in maintaining robust communication under severe external noises such as narrow band interferences and mechanical vibrations, which can disrupt data transmission and require improvements in packet handling and path resolution to ensure reliable data transfer.

Innovation Solution

The implementation of a robust line coding scheme using non-complex bit-to-symbol mapping, forward error correction (FEC) coding, and an additive bit scrambler, along with specific signal constellations and clock structures, to enhance data transmission reliability over communication links like UTP cables in noisy environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional line coding schemes are used, then device complexity is reduced, but reliability deteriorates under severe external noises

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidcoding scheme complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The coding scheme is segmented into distinct functional blocks: bit-to-symbol mapping unit, forward error correction coding unit, and additive bit scrambler unit. Each block performs a specific function to progressively enhance reliability without requiring complete system redesign.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Forward error correction coding is applied preliminarily to the data stream before transmission, preparing the data with error correction capabilities in advance. This preliminary action enables the system to withstand severe noises without requiring complex real-time correction mechanisms.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If robust error correction mechanisms are implemented, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiderror correction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

An additive bit scrambler is introduced as an intermediary component between the bit-to-symbol mapping and the transmitted signal. This scrambler simplifies the error correction process by preprocessing the data with a pseudo-random sequence, making subsequent error correction operations more efficient and less complex.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the parameter of bit scrambling by applying additive scrambling with a specific polynomial (e.g., x^3 + x + 1). This parameter change transforms the data representation in a way that reduces the complexity of subsequent error detection and correction operations while maintaining high reliability.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If high-speed data transmission is achieved, then productivity is improved, but susceptibility to noise increases

Engineering Contradiction:
Improvedata transmission rateVSAvoidnoise susceptibility
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system applies beforehand cushioning by implementing forward error correction coding and bit scrambling before data transmission. These preprocessing steps create a protective buffer against noise, allowing high-speed transmission at 1000 Mbits per second without excessive noise susceptibility.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The additive bit scrambler converts the potential harm of noise into a benefit by spreading the spectral energy of the transmitted signal. This scattering effect reduces the impact of narrowband interferences and impulsive noises, allowing high-speed transmission through noisy environments.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS10447431B2Robust line coding scheme for communication under severe external noises
Publication Date: 2019.10.15 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US10447431B2 patent drawing
  • US10447431B2 patent drawing
  • US10447431B2 patent drawing

AI summary

A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.