PHY Link Synchronization via LPI Timer Offset

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing communication systems fail to synchronize timing between Low Power Idle (LPI) state transitions of Physical Layer (PHY) devices, leading to inefficiencies and lag in the system.

Innovation Solution

Establishing a master-slave relationship between devices to synchronize LPI mode state transitions by using an LPI request signal during link startup, and setting a known offset between LPI QUIET and REFRESH state transitions to avoid overlapping operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If LPI mode is enabled to reduce power consumption, then energy efficiency is improved, but timing synchronization between master and slave devices deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming synchronization

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent performs LPI timer synchronization during link initialization before entering LPI mode. The master device sends an LPI request signal and both devices adjust their LPI timers to start counting at the same time, establishing a known offset. This preliminary synchronization ensures that when LPI mode is later enabled for power savings, the timing synchronization is already established and maintained.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If LPI timer synchronization is performed during link establishment, then timing synchronization is improved, but link setup time increases

Engineering Contradiction:

Improvetiming synchronizationVSAvoidlink setup time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent combines LPI timer synchronization with the existing link initialization sequence. The LPI request signal and timer synchronization steps are integrated into the standard link establishment process rather than being performed as separate operations. This merging allows timing synchronization to be achieved without significantly extending the overall link setup time.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If LPI QUIET and REFRESH operations are performed without offset, then device complexity is reduced, but operation conflicts increase

Engineering Contradiction:

Improvecontrol logicVSAvoidoperation coordination

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent introduces a known asymmetric offset between the LPI timers of master and slave devices during synchronization. This deliberate asymmetry ensures that LPI QUIET and REFRESH operations occur at different times on each device, preventing operation conflicts while maintaining relatively simple control logic. The offset is established once during initialization and then maintained automatically.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS12289387B2Low power idle PHY link synchronization

Publication Date: 2025.04.29 ANALOG DEVICES INT UNLTD CO

AI summary

Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.