PHY Interface MACsec Processing Without TSN Timing Disruption

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Solution Overview

Problem

Implementing higher-layer processing at a physical-layer-interface device can disrupt the timing of time-sensitive data blocks or render them too short, particularly when protocols like MACsec are applied, affecting the performance of time-sensitive networking protocols.

Innovation Solution

The solution involves implementing higher-layer processing, such as MACsec, at the physical-layer-interface device without disrupting time-sensitive operations by adjusting the inter-frame gaps or adding dummy data to maintain the timing integrity of the data blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If higher-layer processing (e.g., MACsec) is implemented at the physical-layer-interface device, then security and data integrity are improved, but the timing of time-sensitive data blocks is disrupted

Engineering Contradiction:

Improvedata securityVSAvoidtiming of data blocks

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by adding dummy data to data blocks before they are processed by higher-layer protocols like MACsec. This pre-padding ensures that when security tags and integrity check values are added, the original timing characteristics of time-sensitive data blocks are preserved, preventing timing disruption while maintaining security requirements

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If higher-layer processing is implemented at the physical-layer-interface device, then processing capability is improved, but data blocks become too short or are disrupted

Engineering Contradiction:

Improveprocessing capabilityVSAvoiddata block length

Core Design Contradiction:

Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The patent uses preliminary action by pre-padding data blocks with dummy data before higher-layer processing. This ensures that when security tags and other protocol elements are added during MACsec processing, the data blocks maintain adequate length and structure, preventing them from becoming too short while enabling enhanced processing capability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces dummy data as an intermediary element between the original data and the higher-layer processing additions. This intermediary padding serves as a buffer that maintains data block integrity and length requirements while allowing security tags and other protocol elements to be added without disrupting the original data structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12566891B2Higher-layer-processing data in time-sensitive data blocks at a physical-layer-interface device

Publication Date: 2026.03.03 MICROCHIP TECHNOLOGY INC

AI summary

Examples of the present disclosure relate generally to implementing higher-layer processing on time-sensitive data blocks at a physical-layer-interface device. Some examples include logic to perform operations, the operations including providing data blocks to a physical-layer-interface device. The operations may also include adding dummy data into one or more time-sensitive data blocks of the data blocks being provided to the physical-layer-interface device. A size of the dummy data corresponding to a size of higher-layer-processing data. Other example operations may include removing higher-layer-processing data from a first ingressing data block. The other operations may also include removing a portion of the first ingressing data block and adding the portion to a subsequent ingressing data block. A size of the portion corresponding to the size of integrity-detection data. The other operations may also include removing the integrity-detection data from an ingressing data block. Related methods, systems, and devices are also disclosed.