PHY Port Expander Multiplexing SerDes Transceivers
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Solution Overview
Problem
Current high-speed Ethernet switches are limited by the number of serializer/deserializer (SerDes) transceivers on a single die, restricting the number of Ethernet ports they can support, and existing solutions like IEEE 802.1BR and FlexE schemes face inefficiencies in multiplexing data flows across different speeds.
Innovation Solution
Implementing a mechanism to multiplex data flows from multiple Ethernet ports onto a single SerDes circuitry, allowing for the use of multiple independent ports with varying link speeds to be combined into a single high-speed link, enabling efficient data transmission while allowing for flexible port configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more SerDes transceivers are integrated on a single die to increase the number of Ethernet ports, then the port capacity is improved, but the chip area and manufacturing complexity increase significantly
Solution Approach 1:
The patent merges multiple SerDes transceivers into a single integrated unit that can handle multiple Ethernet ports simultaneously. By combining the functionality of multiple transceivers into one shared resource, the system achieves higher port capacity without proportionally increasing chip area, as the shared SerDes infrastructure serves multiple ports through time-division or signal-division multiplexing.
Solution Approach 2:
The SerDes transceiver is designed with multi-functionality to serve multiple Ethernet ports with varying speeds (e.g., 25 Gbps, 40 Gbps, 100 Gbps). A single transceiver unit can dynamically adapt to different port requirements through programmable configuration, allowing one hardware resource to perform multiple functions that would traditionally require separate dedicated transceivers for each port.
2Quantity of substance
If existing multiplexing schemes like IEEE 802.1BR and FlexE are used to multiplex data flows, then port capacity is extended, but the complexity of packet tagging and multiplexing increases
Solution Approach 1:
The patent extracts the multiplexing function from the packet layer and implements it at the signal layer within the SerDes transceiver. By moving the multiplexing operation to the physical signal domain rather than the data link layer, the system eliminates the need for complex packet tagging and processing, reducing overall system complexity while maintaining extended port capacity.
Solution Approach 2:
The invention introduces a signal processing intermediary layer within the SerDes transceiver that handles multiplexing at the signal level. This intermediary mechanism converts multiple data streams into a single physical signal for transmission, avoiding the need for complex packet-level multiplexing protocols and reducing the burden on higher protocol layers.
3Adaptability or versatility
If multiple Ethernet ports with varying link speeds are multiplexed onto a single SerDes, then scalability is improved, but the difficulty of synchronizing and managing different data speeds increases
Solution Approach 1:
The SerDes transceiver incorporates dynamic adjustment capabilities that allow it to adapt to varying data speeds from multiple Ethernet ports in real-time. The system can dynamically reconfigure its internal timing and synchronization parameters to match the speed requirements of different ports, enabling flexible multiplexing without requiring complex manual synchronization mechanisms.
Data Source
AI summary
A physical layer (PHY) device of a switch system of a computing network, a switch system including the PHY device, a tangible non-transitory machine-readable medium to perform operations at the PHY device, and a method to be performed at the PHY device. The PHY device includes a first physical input/output (I/O), and a second physical (I/O), and PHY circuitry coupled between the first I/O and the second I/O. The PHY circuitry includes one of a retimer circuitry or a switch circuitry, and is to: implement a plurality of ports at the first I/O, and a data link at the second I/O; access a plurality of data flows from the plurality of ports at the first I/O; determine a multiplexed data stream from the plurality of data flows by implementing a multiplexing algorithm; and send the multiplexed data stream for transmission from the data link at the second I/O.