PHY Retry Buffering for High-Speed Die-to-Die Interfaces
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Solution Overview
Problem
Existing die-to-die interfaces face challenges in increasing operating speeds due to stringent low bit error rate (BER) requirements, which can lead to high latency and additional burdens on controllers.
Innovation Solution
Implementing physical layer (PHY)-based retry mechanisms that use cyclic redundancy check (CRC) information for error detection and a retry buffer to resend data, allowing the die-to-die interfaces to operate at higher data rates without increasing latency or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low BER requirements are enforced to meet FIT rate, then reliability is improved, but operating speed deteriorates
Solution Approach 1:
The interface is segmented into separate retry logic circuitry and main data path, allowing error handling to be isolated and managed independently from the main data transmission flow, enabling higher operating speeds while maintaining reliability through dedicated error detection and retry mechanisms
Solution Approach 2:
Retry logic circuitry acts as an intermediary between the physical layer and controller, handling error detection and retry operations without burdening the controller, thus enabling faster operating speeds while maintaining the required reliability through intermediate error management
2Reliability
If controller-based retry mechanisms are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The retry logic is extracted from the controller and placed in dedicated retry logic circuitry at the physical layer, reducing controller complexity while maintaining reliability through specialized error handling hardware that operates independently
Solution Approach 2:
The retry logic circuitry provides self-service error handling by autonomously detecting errors through CRC verification and initiating retries without controller intervention, reducing controller complexity while maintaining reliable error recovery
3Reliability
If controller-based retry mechanisms are implemented, then reliability is improved, but latency increases
Solution Approach 1:
CRC verification is performed preliminarily on received data before passing to the controller, and retry operations are initiated immediately by the retry logic circuitry without controller intervention, reducing latency while maintaining reliable error recovery through pre-positioned error handling
4Productivity
If higher data rates are implemented, then productivity is improved, but bit error rate worsens
Solution Approach 1:
The system changes the parameter of error handling by implementing PHY-layer retry logic with CRC verification, allowing higher data rates to be used while maintaining reliability through adjusted error detection and correction parameters at the physical layer
Data Source
AI summary
In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.