PHY Layer Selective Low Power Mode for Ethernet Timing Recovery

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing Ethernet network topologies face energy inefficiencies and latency issues due to the lack of quick timing recovery from idle modes, particularly in legacy systems that do not support Energy Efficient Ethernet (EEE) standards, which are not applicable to existing deployments and introduce latency in high-performance applications.

Innovation Solution

Implementing a dynamic power management system that uses higher layer control policies and integrated switch-PHY processing to enable power savings in IDLE mode, fast recovery from IDLE mode, and maintain IDLE signal requirements, through auto-detection of traffic and configurable power savings modes, reducing latency and energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If Energy Efficient Ethernet (EEE) LPI mode is implemented, then energy consumption during low link utilization is reduced, but timing recovery latency increases and it is not applicable to existing network topologies

Engineering Contradiction:
Improveenergy consumptionVSAvoidtiming recovery latency
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The patent divides the PHY layer into multiple independent functional blocks (analog block, digital block, serializer/deserializer) that can be selectively placed into low power mode. This segmentation allows certain blocks to enter low power mode for energy savings while other blocks remain active to maintain timing recovery capabilities, thus resolving the contradiction between energy consumption and timing recovery latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different power states to different functional blocks within the PHY layer based on their specific requirements. Critical blocks for timing recovery remain in normal power mode while non-critical blocks enter low power mode. This local differentiation allows the system to achieve energy savings without compromising timing recovery performance.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If EEE LPI mode is implemented, then energy consumption is reduced, but compatibility with existing network topologies is lost

Engineering Contradiction:
Improveenergy consumptionVSAvoidcompatibility with existing network topologies
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal power management mechanism that can operate with both EEE-capable and legacy network topologies. The selective power management approach is designed to be topology-agnostic, allowing the system to achieve energy savings in existing deployments regardless of whether the network infrastructure supports EEE LPI mode, thus maintaining broad compatibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If continuous IDLE signal transmission is maintained in legacy systems, then timing recovery is preserved, but energy consumption increases

Engineering Contradiction:
Improvetiming recoveryVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts the timing recovery function from the continuous IDLE signal transmission by dedicating specific functional blocks (separate from the analog block) to handle timing recovery. This allows the analog block to enter low power mode without affecting timing recovery, as the timing recovery blocks remain independently active.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent prepares timing recovery blocks in advance to remain active and ready, independent of the power state of other blocks. This preliminary positioning of timing recovery resources ensures that timing recovery capability is maintained without requiring continuous IDLE signal transmission from all blocks, enabling energy savings in blocks that can be powered down.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8935550B2System and method for selectively placing portions of a physical layer into low power mode
Publication Date: 2015.01.13 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8935550B2 patent drawing
  • US8935550B2 patent drawing
  • US8935550B2 patent drawing

AI summary

A method and system to dynamically manager power in a communication system are provided herein. The method comprises the steps of monitoring a transmit data queue once every first pre-determined period of time and determining whether the transmit data queue is empty for a pre-determined number of times. The method further includes the step of generating a transition state signal to stop de-queuing of data from the transmit queue if the transmit data queue is empty for the pre-determined number of times and selectively operating portions of a Physical Layer (PHY) that are used for functions other than transmitting and receiving an idle signal in a low power mode.