PHYless Die-to-Die IO for Mixed-Pitch Chiplet Interoperability
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in die disaggregation due to the need for custom-designed hard IP in PHY-based IOs, which increases design costs and limits interoperability between chiplets with different bump pitches, hindering scalability and efficiency.
Innovation Solution
The implementation of PHYless die-to-die IO interconnects with uniform shoreline width and variable depth in IO bump maps, allowing for interoperability across different bump pitches and eliminating the need for custom hard IP, using digital cells from standard libraries for simplified circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PHY-based IO design is used, then IO functionality is achieved, but custom hard IP design effort and silicon risk increase significantly
Solution Approach 1:
The patent extracts the physical layer (PHY) functionality from the IO design, separating it into a dedicated embedded bridge die. This allows the main chiplets to use simplified PHYless IO interfaces while the bridge die handles all PHY operations, thereby eliminating custom hard IP design requirements and reducing silicon risk in the main chiplet designs.
Solution Approach 2:
The embedded bridge die acts as an intermediary between chiplets with different bump pitches and packaging technologies. It provides the necessary PHY functionality and signal conditioning, enabling interoperability between diverse chiplet configurations without requiring each chiplet to have custom PHY designs.
2Productivity
If die disaggregation is implemented, then enhanced functionality and yield are achieved, but design costs and complexity increase
Solution Approach 1:
The patent segments the system into independent chiplets that can be manufactured separately using standard processes, then interconnected through an embedded bridge die. This segmentation allows each chiplet to be designed with simplified PHYless IO interfaces, reducing individual design costs while enabling enhanced overall functionality through modular assembly.
Solution Approach 2:
By extracting the complex PHY functionality into a separate embedded bridge die, the patent reduces the design complexity and costs for individual chiplets. The bridge die handles all the complex signal conditioning and PHY operations, allowing chiplets to use simpler, more cost-effective designs while still achieving enhanced overall system functionality.
Data Source
AI summary
Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.