Physical-Address Cache Banking for Parallel Access Without Aliasing
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Solution Overview
Problem
Existing multi-bank caches based on virtual addresses require each bank to connect to all memory channels, leading to increased interconnection costs, power consumption, and degraded processor performance.
Innovation Solution
Partition the cache space into banks based on physical addresses, allowing parallel access and reducing the need for each bank to connect to only one memory channel, with MMU or TLB lookup before writing data to eliminate aliasing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If each bank connects to all memory channels in virtual address-based multi-bank caches, then parallel access capability is achieved, but interconnection complexity and power consumption increase
Solution Approach 1:
The patent segments the cache into banks based on physical addresses rather than virtual addresses, which fundamentally changes the interconnection requirements. This physical address-based segmentation allows each bank to connect to only one memory channel, reducing interconnection complexity while maintaining parallel access capability through the physical address mapping structure.
2Productivity
If each bank connects to all memory channels to support parallel access, then data read/write operations can proceed in parallel, but power consumption increases
Solution Approach 1:
By segmenting the cache into physically-addressed banks, the patent enables parallel data read/write operations across different banks without requiring each bank to maintain multiple memory channel connections. This reduces the overall power consumption of the cache subsystem while preserving parallel processing capability.
3Loss of time
If virtual address-based bank partitioning is used, then cache hit access time is reduced, but aliasing issues occur during data writing
Solution Approach 1:
The patent inverts the traditional approach by using physical addresses for bank partitioning instead of virtual addresses. This inversion eliminates the aliasing problem that occurs with virtual address-based partitioning, as physical addresses uniquely identify memory locations without translation ambiguity. The MMU or TLB performs address translation after the bank selection is made, ensuring accurate data writing while maintaining fast cache access.
Data Source
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AI summary
A cache method and apparatus, an electronic device, a storage medium, and a program product. The cache method includes: partitioning a cache space into a plurality of banks based on physical addresses, wherein the plurality of banks allow parallel access (S11); and in response to a data query request, performing a read/write operation on at least one of the plurality of banks (S12).