Physical Memory Address Clustering for Active-Region Prefetching

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Solution Overview

Problem

Existing memory access technologies face challenges in efficiently managing increasing data demands and latency differences between volatile and non-volatile storage media, particularly in predicting data prefetching due to the overhead of translating offline-generated heat maps to physical addresses.

Innovation Solution

A two-level clustering model is employed to group physical memory addresses adaptively, using clusters and active regions, with a prefetch engine monitoring activity levels and making prefetching decisions based on access profiles to minimize cache misses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in non-volatile memory, then storage capacity increases, but data access speed decreases

Engineering Contradiction:
Improvestorage capacityVSAvoiddata access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The system performs preliminary actions by proactively prefetching data from non-volatile memory to volatile memory before actual access requests occur. The prefetch engine identifies active regions and predicts future access patterns, loading data in advance to eliminate latency when data is needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces volatile memory as an intermediary between non-volatile memory and the processor. Data is transferred from non-volatile memory to volatile memory in advance, creating a buffer that provides fast access to frequently used data while maintaining the large storage capacity of non-volatile memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If prefetching is performed, then data access latency is reduced, but system complexity increases

Engineering Contradiction:
Improvedata access latencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The memory space is segmented into active regions and inactive regions based on access patterns. The system divides memory management into distinct components: a prefetch engine for identifying active regions, a translation engine for address mapping, and a data transfer mechanism. This segmentation simplifies the prefetching logic by focusing only on active regions rather than managing entire memory spaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses the access patterns generated by applications themselves to drive the prefetching process. The prefetch engine monitors actual access behavior and uses this information to automatically identify active regions and trigger prefetching operations, eliminating the need for external control or complex manual configuration.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If heat map translation is performed, then prefetching accuracy improves, but processing overhead increases

Engineering Contradiction:
Improveprefetching accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Instead of translating and processing entire heat maps, the system performs partial action by focusing only on active regions that are actually being accessed. The prefetch engine identifies and processes only the relevant portions of memory space, avoiding the overhead of translating complete heat maps while maintaining prefetching accuracy for the important data.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250284640A1Systems and methods for grouping memory addresses
Publication Date: 2025.09.11 SAMSUNG ELECTRONICS CO LTD
  • US20250284640A1 patent drawing
  • US20250284640A1 patent drawing
  • US20250284640A1 patent drawing

AI summary

Systems and methods for grouping memory addresses are disclosed. A storage device may include a first storage medium, a second storage medium, and a processor configured to: identify a first memory address; identify a first region of the first storage medium based on the first memory address; track activity of the first region; identify a second memory address based on tracking activity of the first region; and retrieve data associated with the second memory address from the first storage medium and store the data in the second storage medium.