Physical Address Memory Paging for Multi-Core Processors
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Solution Overview
Problem
Modern computer systems using paging for memory management face inefficiencies in memory access due to the need for virtual-to-physical address translations, which can be complex and resource-intensive, especially in multi-core processors where shared memory access is required.
Innovation Solution
A system and method where processor cores access system memory using only physical addresses, employing a shared cache subsystem that determines if the address is within a paged region and accesses a shared page attributes table to manage memory access requests, eliminating the need for virtual address translations and translation lookaside buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If virtual-to-physical address translation is used for memory management, then memory utilization efficiency is improved, but device complexity and resource requirements increase due to the need for page tables and translation lookaside buffers
Solution Approach 1:
The patent extracts and eliminates the virtual address translation hardware (page tables and translation lookaside buffers) from the memory management system. By using only physical addresses directly generated by processor cores, the system removes the complex translation layer while maintaining efficient memory utilization through the cache subsystem's direct physical address handling capabilities
Solution Approach 2:
The cache subsystem is enhanced to perform multiple functions: it directly handles physical address translation requests, manages paged and non-paged memory regions, and provides memory access control without requiring separate virtual-to-physical translation hardware. This multi-functional approach consolidates memory management capabilities into a single subsystem, reducing overall device complexity
2Speed
If translation lookaside buffers are implemented to store frequently used virtual-to-physical translations, then memory access speed is improved, but area and resource requirements increase
Solution Approach 1:
The patent removes the translation lookaside buffer component entirely from the system. Since virtual addresses are not used and only physical addresses are generated by processor cores, there is no need for translation buffering. The cache subsystem directly handles physical address accesses, eliminating the area requirements for translation buffers while maintaining fast memory access through its inherent caching capabilities
3Adaptability or versatility
If virtual address translation structures are implemented in the processor, then address mapping flexibility is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent extracts and eliminates the power-consuming virtual address translation structures from the processor. By using only physical addresses, the system removes the energy-intensive translation process while maintaining address mapping flexibility through the cache subsystem's ability to handle both paged and non-paged memory regions using physical addresses directly
Solution Approach 2:
The cache subsystem is designed to self-manage memory access operations using physical addresses directly from processor cores. It autonomously determines whether addresses fall in paged or non-paged regions and handles the appropriate memory management operations without requiring additional power-consuming translation hardware or processes
Data Source
AI summary
A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.