Physical Address Proxies for Cache-Line-Straddling Load/Store Access
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Solution Overview
Problem
Cache memories in microprocessors significantly impact performance due to access time and cache coherency issues, particularly in multi-processor systems, leading to inefficiencies and idle execution units.
Innovation Solution
Implementing a physically-indexed, physically-tagged second-level set-associative cache with store and load queues that utilize physical address proxies (PAPs) to manage cache lines and enhance cache coherency, allowing efficient handling of cache line boundary-straddling load/store instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to improve processor performance, then access time is reduced, but cache coherency issues arise in multi-processor systems
Solution Approach 1:
The patent introduces an intermediary mechanism (cache coherency protocol with physical address proxies) that mediates between multiple processors and the cache system, enabling fast access while maintaining coherency through coordinated address translation and validation
2Speed
If store data is written to cache memory, then write speed is improved, but handling data that straddles cache line boundaries causes performance penalties
Solution Approach 1:
The patent segments the store data into portions that fit within cache line boundaries, using physical address proxies to identify and separate data that would otherwise straddle boundaries, allowing efficient cache-line-aligned writes while maintaining correctness for straddling stores
Solution Approach 2:
The patent changes the parameter representation by using physical address proxies instead of full physical addresses, enabling the system to detect and handle cache line boundary conditions through parameter transformation and comparison
3Measurement precision
If full physical addresses are stored in cache entries, then address accuracy is improved, but cache entry size and physical cache size increase
Solution Approach 1:
The patent extracts only the necessary portions of the physical address (physical address proxies) and stores them in cache entries, removing redundant address information while retaining sufficient precision for coherency checking and address translation
4Reliability
If cache capacity is increased to improve hit rate, then more data can be cached, but cache access time and cycle time increase
Solution Approach 1:
The patent changes the address representation parameter to use compact physical address proxies, enabling larger cache capacity within the same physical footprint while maintaining fast access times through efficient address comparison and tagging
Data Source
AI summary
A microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. A set index and a way uniquely identifies each entry. A load/store unit, during store/load instruction execution: detects that a first and second portions of store/load data are to be written/read to/from different first and second lines of memory specified by first and second store physical memory line addresses, writes to a store/load queue entry first and second store physical address proxies (PAPs) for first and second store physical memory line addresses (and all the store data in store execution case). The first and second store PAPs comprise respective set indexes and ways that uniquely identifies respective entries of the second-level cache that holds respective copies of the respective first and second lines of memory. The entries of the store queue are absent storage for holding the first and second store physical memory line addresses.