Physical-Aware ATPG for Small Delay Defect Detection
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Solution Overview
Problem
Current methods for detecting Small Delay Defects (SDDs) in Integrated Circuits (ICs) are inefficient due to their inability to effectively identify defects in complex ICs, leading to false rejection of good ICs and increased power consumption, especially as IC feature sizes increase, causing performance slowdowns.
Innovation Solution
A physical-aware Automatic Test Pattern Generation (ATPG) method that classifies IC paths and nets into susceptible and non-susceptible groups based on physical parameters, applying a hybrid test pattern set using timing-aware and Transition Delay Fault methods to achieve high coverage and efficiency in SDD detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Faster-than-at-speed delay tests are used to detect SDDs by removing slack time, then SDD detection capability is improved, but power consumption increases beyond maximum specified values and additional design constraints are required
Solution Approach 1:
The patent changes the test frequency parameter from higher-than-operational (Faster-than-at-speed) to operational or lower frequencies. The method uses operational frequency testing with specific test patterns that target critical paths, thereby maintaining SDD detection capability while keeping power consumption within specified maximum values.
Solution Approach 2:
The patent applies different testing strategies to different parts of the IC circuit. Instead of uniformly testing all paths at high frequency, it identifies and targets only the critical paths and vulnerable circuits that are most susceptible to SDDs, applying localized test patterns that achieve high detection coverage with minimal power consumption.
2Reliability
If timing-aware ATPG method is used to excite SDDs through long paths, then SDD detection coverage is improved, but pattern count and run time increase exponentially
Solution Approach 1:
The patent segments the IC circuit into critical paths and non-critical paths based on timing analysis. It then applies timing-aware ATPG methods only to the identified critical paths that are most vulnerable to SDDs, rather than applying the method to all paths in the circuit. This segmentation dramatically reduces the pattern count and run time while maintaining high detection coverage.
Solution Approach 2:
The patent applies partial action by using timing-aware ATPG on only the necessary critical paths rather than all paths. It identifies a subset of long paths that are most vulnerable to SDDs and applies the computationally intensive timing-aware method only to those paths, achieving sufficient detection coverage without exponential increase in overall test time.
3Ease of operation
If traditional TDF method is used for testing, then test simplicity is maintained, but SDD detection capability is insufficient due to small delay variations being within specifications
Solution Approach 1:
The patent performs preliminary timing analysis and critical path identification before applying test patterns. By pre-identifying the critical paths and vulnerable circuits that are most susceptible to SDDs, the method prepares targeted test patterns in advance, maintaining operational simplicity while significantly improving SDD detection capability compared to traditional TDF methods.
Data Source
AI summary
System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.