Physical-Aware Memory Test Scheduling for Local IR Drop Control
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Solution Overview
Problem
Parallel memory testing in SoC designs leads to peak current-induced voltage drops (IR drop) and increased test costs due to excessive localized current demands, potentially rejecting or downgrading good dice and requiring additional power supplies.
Innovation Solution
Optimize memory test sequencing by creating scheduling buckets with serially executed test sequences, reordering them based on physical characteristics to reduce local IR drops and overall peak current demands, using algorithms like bin packing and greedy search to maximize physical separation of memory groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memories are tested in parallel, then test time is reduced, but peak current increases causing voltage drops (IR drop)
Solution Approach 1:
The patent applies dynamic scheduling by adjusting the start times of test sequences based on power consumption profiles. Instead of static parallel execution, the system dynamically determines when to start each test sequence to avoid peak current overlap, thereby reducing IR drop while maintaining high productivity through optimized parallel execution windows.
Solution Approach 2:
The patent implements periodic action by dividing test sequences into multiple time periods or phases. Tests are scheduled in periodic waves where the start time of each subsequent test is offset from previous tests, creating a staggered execution pattern that distributes current demand over time while still achieving parallel testing benefits.
2Productivity
If memories are tested in parallel, then overall test efficiency increases, but localized current demands become excessive
Solution Approach 1:
The patent applies local quality by considering the physical location and power consumption characteristics of individual memory groups. The scheduling algorithm assigns different start times to test sequences based on their specific power profiles and physical locations on the chip, thereby locally optimizing current distribution and preventing excessive localized current demands in specific regions.
3Reliability
If additional power supplies are added to handle peak current, then voltage stability improves, but test cost increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-scheduling test sequences to avoid peak current conditions before testing begins. The power profile analysis and scheduling optimization are performed in advance, creating a test plan that inherently prevents voltage instability without requiring additional power supply infrastructure, thereby maintaining reliability while avoiding increased complexity and cost.
Data Source
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AI summary
A method for physical-aware power profile optimization during memory test includes creating a plurality of scheduling buckets, wherein each scheduling bucket includes one or more sequentially executed test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence including a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to a test time budget. A power profile is optimized by determining a respective optimized start time of at least one test sequence from at least a physical distance between two groups of memories controlled by respective BIST controllers. The respective optimized start time is assigned to the at least one test sequence.