Physical Awareness in Semiconductor Fabrication Test Patterns
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Solution Overview
Problem
Current semiconductor device fabrication methods lack effective means to validate physical design margins and verify faults accommodated by functional patterns, as functional verification is not aware of physical design structures, leading to inefficient and potentially false test results due to the lack of physical awareness in testing processes.
Innovation Solution
A method that identifies targets with transitional sensitivity, generates verification models, creates and translates patterns into assertions, runs formal verification, and translates assertions into coverage events to create manufacturing tests that account for physical properties, thereby reducing test time and improving the effectiveness of FBIST tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional verification is performed without physical awareness, then verification can be completed, but test effectiveness is reduced and false results may occur
Solution Approach 1:
The patent merges functional verification with physical design awareness by integrating physical design structure information into the functional verification process. This combination allows the verification to simultaneously consider functional requirements and physical constraints, eliminating the information loss that occurs when verification is performed in isolation from physical design data.
2Reliability
If comprehensive testing of all functional patterns is performed, then coverage is improved, but test time increases significantly
Solution Approach 1:
The patent extracts and identifies only those functional patterns that are critical for testing physical design margins and transitions. By separating the essential test patterns from the complete functional pattern set, the method achieves adequate test coverage while significantly reducing test time compared to comprehensive testing of all patterns.
Solution Approach 2:
The patent applies local quality by focusing testing resources on specific critical paths and transitions that are most sensitive to physical design variations. Instead of uniform testing across all functional patterns, the method concentrates test effort on locally critical areas where physical awareness indicates higher risk or importance.
Data Source
AI summary
A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.