Physical Interface Error Detection for Serial IC Links
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Solution Overview
Problem
Conventional physical interfaces are inadequate for timely and reliable error detection and correction in asynchronous and serial data communications, as they are optimized for synchronous and parallel data transfers, leading to increased errors due to background noise and delayed error detection.
Innovation Solution
A physical interface apparatus and method that facilitates error detection and optional correction within the physical layer, using a decoder to extract error detection bits from encoded data and generate error-detection codes, allowing for early error detection and correction before reaching upper layers, and includes error recovery modules to retransmit or correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional physical interfaces use synchronous and parallel data communications, then data transfer reliability is maintained, but they cannot readily be adapted to asynchronous and serial data communications which require timely error detection
Solution Approach 1:
The patent segments the error detection function by extracting error detection bits separately from the data bits during decoding. The physical interface decoder extracts error detection bits and passes them to a physical interface error detector, which operates independently from the main data processing path. This segmentation enables timely error detection in serial asynchronous communications while maintaining the reliability benefits of separate error handling.
Solution Approach 2:
The patent introduces a physical interface error detector as an intermediary component between the decoder and upper-layer error detection mechanisms. This intermediary extracts and detects errors at the physical layer before data proceeds to higher layers, enabling timely error detection for serial asynchronous communications without compromising the reliability framework of the system.
2Reliability
If error detection and correction are performed at the data link layer or upper layers, then comprehensive error checking is achieved, but computational resources are increased and communication delays occur
Solution Approach 1:
The patent performs preliminary error detection at the physical interface layer before data proceeds to upper layers. By extracting and detecting errors early in the reception process, the system avoids the need for extensive computational resources at higher layers, reducing overall device complexity while maintaining comprehensive error detection capability.
Solution Approach 2:
The patent extracts error detection bits from the received data stream at the physical interface level and handles them separately through a dedicated error detector. This extraction approach enables simple, low-resource error detection at the physical layer, reducing the computational burden on upper layers while maintaining reliable error detection across the entire data path.
3Use of energy by moving object
If conventional serial data links reduce noise and power, then energy efficiency is improved, but they become susceptible to data corruption during transit
Solution Approach 1:
The patent implements beforehand cushioning by incorporating error detection bits into the transmitted data stream before transmission occurs. These pre-inserted error detection bits provide a protective mechanism that detects data corruption caused by noise in low-power serial communications, maintaining data integrity without requiring increased transmission power.
Solution Approach 2:
The patent uses error detection bits as a form of redundant information that copies verification data along with the main data stream. This copying approach enables the receiver to verify data integrity without retransmitting the entire data stream, maintaining energy efficiency while protecting against data corruption in low-power serial communications.
Data Source
AI summary
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.