Physical Interface Error Detection for Serial IC Links
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Solution Overview
Problem
Conventional physical interfaces are not well-suited for timely and reliable error detection and correction in asynchronous and serial data communications, leading to data corruption and increased computational resources spent on processing incorrect data bits.
Innovation Solution
A physical interface that facilitates error detection and optional correction at the physical layer, using error detection bits interleaved with application data bits, allowing for early error detection and correction without requiring application-specific error handling, and includes an error corrector to request retransmissions or signal errors to application-specific modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional physical interfaces transmit data bits at faster data rates and decreasing amplitudes, then data transmission speed is improved, but signal-to-noise ratio decreases leading to increased errors
Solution Approach 1:
The patent applies preliminary action by inserting error detection bits into the data stream before transmission occurs. These error detection bits are positioned strategically within the encoded data bits, allowing the receiver to detect and correct errors as data is being received, rather than waiting for complete data frames. This proactive error detection mechanism compensates for the decreased signal-to-noise ratio that results from transmitting at higher speeds with lower amplitudes.
2Reliability
If error detection and correction are performed at the data link layer beyond the physical interface, then error detection capability is provided, but error detection time is delayed
Solution Approach 1:
The patent applies segmentation by dividing the error detection function into two parts: physical layer error detection using error detection bits inserted within the data stream, and data link layer error detection using traditional CRC codes. This segmentation allows error detection to occur at multiple levels simultaneously, with the physical layer providing immediate detection of individual bit errors as they are received, while the data link layer provides comprehensive frame-level error detection.
Solution Approach 2:
By inserting error detection bits within the encoded data stream during the physical layer encoding process, the patent enables error detection to occur concurrently with data reception rather than waiting for complete frames. This preliminary error detection at the physical layer reduces the overall error detection time while maintaining robust error detection capability.
3Productivity
If conventional physical interfaces are optimized for synchronous and parallel data communications, then synchronous communication efficiency is improved, but adaptability to asynchronous and serial data communications is reduced
Solution Approach 1:
The patent applies universality by designing a physical interface error detection mechanism that works effectively with both synchronous and asynchronous communication modes, as well as with both parallel and serial data links. The error detection bits are integrated into the existing encoding schemes (such as 8B/10B encoding) used in high-speed serial interfaces like SATA and PCI Express, allowing the same error detection infrastructure to serve multiple communication protocols and modes without requiring separate specialized error handling mechanisms for each.
4Reliability
If error detection codes are appended to follow encoded data bits, then complete error detection can be performed, but transmission time for error detection codes increases
Solution Approach 1:
The patent applies merging by combining error detection bits with the encoded data bits in the same transmission stream. Instead of separating error detection codes into distinct fields that are transmitted after data, the error detection bits are interleaved with the data bits during encoding. This merging allows error detection functionality to be embedded within the data stream itself, eliminating the need for separate error detection code transmission and reducing overall transmission time.
Solution Approach 2:
By inserting error detection bits into the data stream during the encoding process rather than appending them after transmission, the patent enables error detection to occur concurrently with data reception. This preliminary integration of error detection bits into the encoded stream reduces the total time required for error detection while maintaining complete error detection capability.
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits ("ICs") are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface ("PI") error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.