Physical-Layer Key Interleaving for Low-Overhead Wireless Security

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Solution Overview

Problem

Existing secure block interleaving schemes for Direct-Sequence Code Division Multiple Access and orthogonal frequency division multiple access systems are vulnerable to eavesdropping and brute-force attacks, with high hardware overhead and limited ability to update interleaver mapping, and they do not effectively secure communication against adversaries.

Innovation Solution

The Phy-Leave technique implements a flexible, low-overhead interleaver with a time-varying key at the physical layer, allowing rapid key updates and secure data transmission, while PilotCrypt rearranges data and pilot tone sub-carriers using a secret key, providing high flexibility and reducing the effectiveness of brute-force attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If AES based interleaving is used to secure wireless communication, then security is improved, but hardware overhead and computational complexity increase significantly

Engineering Contradiction:
Improvecommunication securityVSAvoidhardware overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of the interleaving approach from AES-based cryptographic operations to a simpler permutation-based scheme using pseudo-random sequences. This parameter change maintains security functionality while dramatically reducing hardware complexity and computational overhead, making it suitable for resource-constrained wireless devices.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs lightweight pseudo-random sequences instead of expensive AES cryptographic operations. These simpler sequences can be generated and discarded more easily, reducing the need for complex hardware resources while maintaining the security function through frequent key updates.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If AES operations are performed to generate row and column indices, then interleaving security is improved, but the ability to rapidly update interleaver mapping is degraded

Engineering Contradiction:
Improveinterleaving securityVSAvoidkey update speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent changes the computational parameter from expensive AES operations to efficient pseudo-random sequence generation. This allows the system to maintain secure interleaving while updating keys rapidly, as the simpler mathematical operations can be executed much faster and with fewer computational resources.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic key updating capability by using a flexible pseudo-random sequence generator that can be reconfigured quickly. This dynamic approach allows the interleaver mapping to be updated in real-time without the computational burden of AES rekeying, enhancing both security and adaptability.

Inventive Principle:
Principle #15Dynamics

3Reliability

If fixed point data interleaving is performed, then security against eavesdropping is improved, but memory overhead increases due to 16-bit storage requirements

Engineering Contradiction:
Improveeavesdropping resistanceVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the data representation parameter from fixed-point format requiring 16-bit storage to a more efficient format that reduces memory requirements. This parameter optimization maintains the security function while significantly reducing the memory overhead, making the system suitable for devices with limited memory resources.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses efficient data structures and representations that minimize memory usage while preserving the security properties of the interleaving scheme. By optimizing the data format used for storing and processing interleaved information, the system achieves both security and memory efficiency.

Inventive Principle:
Principle #26Copying

4Ease of operation

If plaintext and key are transmitted for each row and column index, then receiver synchronization is improved, but vulnerability to interception and brute-force attacks increases

Engineering Contradiction:
Improvereceiver synchronizationVSAvoidadversary interception capability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the plaintext from the transmission process entirely. Instead of transmitting plaintext along with key information, the system uses only the pseudo-random sequence generator key at the transmitter, which the receiver independently reproduces. This extraction of plaintext eliminates the interception vulnerability while maintaining synchronization through the shared key mechanism.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a pseudo-random sequence as an intermediary between the transmitted data and the decryption process. This intermediary allows the receiver to synchronize and decode without receiving the actual plaintext or key transmission, as the pseudo-random sequence serves as a shared secret that both parties generate independently.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11540120B2Physical layer key based interleaving for secure wireless communication
Publication Date: 2022.12.27 DREXEL UNIV
  • US11540120B2 patent drawing
  • US11540120B2 patent drawing
  • US11540120B2 patent drawing

AI summary

A key-based interleaver for enhancement the security of wireless communication includes a physical layer communication channel key to provide security even when the software encryption key is compromised. A method of creating a secure communication link using a physical layer interleaving system includes implementing a key policy implementation that utilizes temporal dependency and interleaving bits using a flexible inter and intra-block data interleaver.