Physical Layer Loopback for PCI Express Fault Isolation
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Solution Overview
Problem
Existing loopback techniques in chip communication rely on software-initiated signals, which can mask failures and impair product validation due to lack of isolation of exact failing conditions, making it difficult to accurately test and debug chip interactions.
Innovation Solution
Implementing a physical layer-controlled loopback mechanism that allows chips to enter loopback mode independently of operating systems, using control circuitry and mode controlling registers to manage signal timing and voltage, enabling direct interconnect access for testing and validation without software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-initiated loopback signals are used, then loopback functionality can be implemented, but failure masking occurs and product validation is impaired
Solution Approach 1:
The patent replaces software-based loopback initiation with a physical layer mechanism. Specifically, it uses dedicated physical interconnects (separate from data carriers) and hardware-controlled loopback mode to initiate and control loopback testing. This substitution eliminates the masking effect caused by software error correction, enabling precise fault isolation at the physical layer without intervention from higher-level software error handling mechanisms.
2Productivity
If operating system control is used for loopback, then loopback can be initiated, but high-volume testing without full PC platform becomes difficult
Solution Approach 1:
The patent segments the loopback control function from the operating system and software layers, placing it directly at the physical layer of the chip interconnect. This segmentation allows loopback testing to be performed independently without requiring a fully functional PC platform or operating system, thereby enabling high-volume testing with reduced system complexity and increased productivity.
3Speed
If inband interconnects are used for loopback, then signal transmission occurs, but common mode voltage passes along with differential signals
Solution Approach 1:
The patent separates the control function from the data transmission function by using dedicated physical interconnects for loopback control that are distinct from the inband data carriers. This segmentation allows the implementation of common mode voltage rejection techniques on the control interconnects without impacting the high-speed data transmission on the inband interconnects, thereby eliminating harmful common mode voltage while preserving signal transmission speed.
Data Source
AI summary
In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.