Physical Layer RC Matching for CAN Bus EMC Immunity

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Solution Overview

Problem

Integrated circuits used in differential network bus nodes face challenges with low frequency resonance and increased power injection due to reduced equivalent capacitance in minimal CAN networks, leading to reduced EMC performance, especially at high frequencies, as specified in the latest IEC62228-3:2019 standard.

Innovation Solution

The integrated circuit incorporates physical layer interface circuits with low and high frequency RC matching circuits to shift low frequency resonance to lower frequencies, reduce its quality factor, and decrease high frequency impedance, thereby reducing power injection into the IC. These circuits are optimized and positioned within the pad ring of the IC, allowing for connection to an external common mode choke and network bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a minimal CAN network with only two nodes is used, then the equivalent capacitance of the CAN bus is reduced, but the amount of power injected into the IC increases and EMC performance deteriorates

Engineering Contradiction:
Improvenetwork simplicityVSAvoidpower injection and EMC performance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent modifies the electrical parameters of the bus by introducing RC matching circuits that change the equivalent capacitance and impedance characteristics. The circuits adjust the frequency-dependent impedance to reduce power injection at resonance frequencies while maintaining proper signal transmission in the minimal two-node network configuration.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The RC matching circuits act as intermediary elements between the transceiver and the CAN bus. These circuits mediate the interaction by providing impedance transformation and filtering, thereby reducing the harmful power injection into the IC while preserving the benefits of the minimal network topology.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If an external CMC is connected to the IC, then low frequency resonance around 4 MHz is generated, but power injection increases and receiver immunity decreases

Engineering Contradiction:
Improveimmunity specification complianceVSAvoidpower injection at resonance frequency
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful resonance effect into a beneficial filtering mechanism. The RC matching circuits are designed to resonate at the same frequency as the CMC-IC capacitance combination, but with opposite phase characteristics, thereby canceling the harmful power injection while maintaining the low-frequency immunity protection provided by the CMC.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces asymmetric RC matching circuits with different resistance and capacitance values optimized for specific frequency ranges. The circuits create an asymmetric impedance profile that suppresses the symmetric resonance peak caused by the CMC, thereby reducing power injection while maintaining immunity at other frequencies.

Inventive Principle:
Principle #4Asymmetry

3Object-affected harmful factors

If RC matching circuits are added to the physical layer interface, then immunity performance and EMC compliance are improved, but device complexity increases

Engineering Contradiction:
Improveimmunity performanceVSAvoidphysical layer interface circuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the RC matching circuits directly into the physical layer interface structure, integrating them with the existing transceiver architecture. This consolidation achieves improved immunity performance while minimizing the increase in device complexity by sharing common elements and optimizing the overall interface design.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies RC matching circuits selectively at critical interface points where impedance matching is most needed, rather than uniformly across the entire system. This localized approach improves immunity performance at specific frequency ranges while keeping the overall device complexity manageable by avoiding unnecessary circuitry in non-critical areas.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively improves immunity performance by reducing power injection at resonance frequencies and high frequencies, ensuring compliance with EMC standards and preventing IC failure during direct power injection tests, while maintaining existing IC architecture and reducing die size.

Implementation Method 1

A 100 uH CMC together with the equivalent capacitance of the IC can generate a low frequency resonance around 4 MHz

Methodology Applied
Scientific EffectResonance: Resonance

Implementation Method 2

a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal

Methodology Applied
Scientific EffectRC time constant:

Implementation Method 3

decrease high frequency impedance to decrease the level of power injected into the IC

Methodology Applied
Scientific EffectImpedance:

Data Source

PatentEP3742678B1Integrated circuit with physical layer interface circuit
Publication Date: 2022.02.23 NXP USA INC
  • EP3742678B1 patent drawingFigure 1~2
  • EP3742678B1 patent drawingFigure 3
  • EP3742678B1 patent drawingFigure 4~5

AI summary

An integrated circuit (202) for use in a differential network bus node (200) comprising: a transceiver (212) having a first transceiver input-output terminal (214) and a second transceiver input-output terminal (216); a physical layer high terminal (208) connected to the first transceiver input-output-terminal (214); a physical layer low terminal (210) connected to the second transceiver input-output terminal (216); and a physical layer interface circuit (234) comprising: a first low frequency RC matching circuit (236) and a first high frequency RC matching circuit (240) each connected between the first transceiver input-output-terminal (214) and a first reference terminal (238); and a second low frequency RC matching circuit (242) and a second high frequency RC matching circuit (246) each connected between the second transceiver input-output terminal (216) and a second reference terminal (244).