Physical Layer Block Coding for RS-FEC Hamming Distance
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Solution Overview
Problem
The 64B/66B encoding method used in 100G Ethernet is inadequate for meeting the requirements of the RS-FEC algorithm, particularly in high-speed interfaces and high-order modulation technologies, as it cannot provide sufficient Hamming distance and checksum space for error correction in advanced Ethernet standards like 400G Ethernet.
Innovation Solution
A physical layer encoding and decoding method that compresses control blocks in 256-bit blocks to create a 256B/257B or 256B/258B encoding scheme, using multiple levels of block type fields and sync headers to ensure a Hamming distance of at least 4, allowing for efficient error correction with RS-FEC algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 64B/66B encoding is used in 100G Ethernet, then the encoding can be implemented with simpler structure, but the Hamming distance and checksum space are insufficient for RS-FEC algorithms in 400G Ethernet
Solution Approach 1:
The patent changes the encoding parameters from 64B/66B to 256B/257B or 256B/258B, increasing the block size and adjusting the ratio to provide sufficient checksum space (at least 4 bits) for RS-FEC algorithms while maintaining encoding efficiency. This parameter change enables both adequate error correction capability and reasonable structural complexity.
2Reliability
If control blocks are compressed to create space for checksum, then the Hamming distance increases to at least 4, but the encoding complexity increases with multiple levels of block type fields
Solution Approach 1:
The patent segments the 256-bit block into multiple 64-bit sub-blocks, each with its own control block. By compressing control blocks (converting 8-bit control blocks to 7-bit or shorter), space is created for additional checksum bits. The block type fields are hierarchically organized to manage the complexity of identifying control vs. data blocks across multiple levels.
Solution Approach 2:
The patent introduces a hierarchical dimension to the block type field structure, with first-level and second-level block type fields. This multi-dimensional approach allows the system to distinguish between control and data blocks while providing sufficient bits for checksum, resolving the conflict between Hamming distance requirements and encoding complexity.
3Reliability
If 256-bit blocks are used instead of 64-bit blocks, then sufficient checksum space is provided for RS-FEC, but the processing overhead and complexity increase
Solution Approach 1:
The patent merges four 64-bit blocks into a single 256-bit super-block structure, allowing centralized control block compression and unified checksum generation. This merging reduces the total number of control blocks that need individual processing compared to handling four separate 64-bit blocks, thereby improving processing efficiency while maintaining sufficient checksum space.
Data Source
Figure 1~2A
Figure 2B
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AI summary
This application discloses a physical layer encoding and decoding method and apparatuses thereof, where the method includes: receiving an MII control block and a first 256-bit to-be-encoded block that are input; determining a control block in the first 256-bit to-be-encoded block, and compressing the determined control block; determining a physical layer encoding format, a value of a sync header, a hierarchy of a block type field, and a value of the block type field according to the MII control block; and obtaining an encoding result by means of mapping the compressed to-be-encoded block to data in a physical layer data format according to the determined physical layer encoding format, adding a sync header to the data, and adding, according to the hierarchy of the block type field, a block type field to space obtained by compression. This application may be used to meet a requirement of an RS-FEC algorithm.