Automated Physical Memory Identification via Chip Select Tracing

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Solution Overview

Problem

The complexity of identifying and testing physical memories within intellectual property cores, especially with varying configurations of logical and physical memory arrangements, poses challenges in ensuring proper functionality and quality, as existing methods lack automation for determining physical memories associated with logical memories and their enabling signals.

Innovation Solution

A method involving the receipt of a generic netlist, generation of a test mode, simulation, and identification of physical memories by tracing chip selects and address/data pins, utilizing both synthesis and test tools to automate the process of mapping logical to physical memories and determining enabling signals, thereby facilitating accurate testing and validation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If manual identification methods are used to determine physical memories and their associations with logical memories, then flexibility in handling different customer configurations is maintained, but the process becomes time-consuming and error-prone

Engineering Contradiction:

Improvemanual identification processVSAvoidtime to identify physical memories

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The system performs self-identification of physical memories by automatically tracing chip select signals and decoding logic relationships without requiring manual intervention. The automated methodology extracts and analyzes netlist information to independently determine the mapping between logical and physical memories, eliminating the need for manual configuration while maintaining accuracy across different customer implementations.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The manual mechanical process of identifying and tracing memory associations is replaced with an automated electronic analysis system. The methodology uses computer-based tools to automatically trace chip select signals through the design netlist, decode logic relationships, and generate memory mapping information, substituting human manual effort with automated electronic verification processes.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If automated identification methods are implemented to determine physical memories, then time and accuracy are improved, but the complexity of the identification process increases

Engineering Contradiction:

Improveaccuracy of physical memory identificationVSAvoidcomplexity of identification process

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The complex identification process is segmented into distinct automated phases: extracting netlist information, identifying chip select signals, tracing signal paths, decoding logic relationships, and generating memory mapping results. Each phase handles a specific aspect of the identification task, making the overall complex process manageable and systematic while maintaining high accuracy through structured automated analysis.

Inventive Principle:

Principle #1Segmentation

3Measurement precision

If detailed tracing of chip selects and address/data pins is performed to ensure accurate identification, then identification accuracy is improved, but the computational effort and process complexity increase

Engineering Contradiction:

Improveidentification accuracyVSAvoidspeed of identification process

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The system performs preliminary extraction and organization of netlist information before conducting detailed tracing operations. By pre-identifying relevant chip select signals and their associated logic relationships in advance, the system prepares the data structure to enable efficient subsequent tracing of address and data pins, reducing redundant computational effort while maintaining comprehensive identification accuracy.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10699795B1System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property cores

Publication Date: 2020.06.30 CADENCE DESIGN SYST INC

AI summary

A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.