Physical Memory Fault Table for Dynamic Error Mapping
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Solution Overview
Problem
Information handling systems face challenges in preventing bad memory access, which can lead to errors and inefficiencies due to variations in memory usage and error thresholds, requiring effective methods to monitor and manage memory errors.
Innovation Solution
The implementation of a physical memory fault table (PMFT) that allocates bits to represent memory blocks, monitors memory errors, and dynamically changes bit values based on error counts, allowing the system to mark and avoid error-prone memory areas, with mechanisms to translate single-bit errors to physical addresses and generate alerts for the operating system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory is continuously monitored and dynamically mapped for errors, then system reliability is improved, but device complexity increases due to the physical memory fault table and monitoring mechanisms
Solution Approach 1:
The patent segments the memory space into manageable blocks and uses a physical memory fault table (PMFT) where each bit represents a specific memory block. This segmentation allows the system to track errors at a granular level without monitoring every single memory address individually, thus improving reliability while controlling complexity through structured division of the memory monitoring task.
Solution Approach 2:
The patent introduces a physical memory fault table (PMFT) as an intermediary data structure between the memory hardware and the operating system. This PMFT acts as a mediator that translates physical memory addresses into fault status information, allowing the system to manage memory errors without requiring complex direct monitoring of all memory operations, thereby resolving the contradiction between reliability and complexity.
2Productivity
If error-prone memory areas are dynamically mapped and avoided, then productivity is improved by preventing bad memory access, but measurement precision is required to accurately detect and locate memory errors
Solution Approach 1:
The patent implements preliminary error detection and mapping by continuously monitoring memory blocks and updating the physical memory fault table (PMFT) before bad memory access occurs. By proactively identifying and marking error-prone areas in advance, the system prevents productivity losses from bad memory access without requiring complex real-time analysis, thus balancing productivity improvement with manageable measurement precision requirements.
Solution Approach 2:
The patent replaces complex mechanical or software-based memory error detection mechanisms with a streamlined bit-mapping approach using the PMFT. Instead of requiring sophisticated error analysis systems, the patent uses simple bit flags in the PMFT to represent memory block status, substituting complex measurement systems with a more manageable bitwise representation that still provides sufficient precision for error avoidance.
3Loss of information
If the physical memory fault table dynamically tracks memory errors, then loss of information is reduced by avoiding bad memory access, but the system requires additional memory resources to maintain the fault table
Solution Approach 1:
The patent changes the parameter representation of memory status by using a compact bit-mapped format in the PMFT instead of traditional error logging structures. Each bit in the PMFT represents the status of a memory block, allowing the system to track potential information loss across the entire memory space using minimal storage resources. This parameter change from detailed error records to compact bit flags resolves the contradiction between preventing information loss and conserving memory resources.
Data Source
AI summary
An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.