Physically Adjacent Row Mapping for Row-Hammer Mitigation
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Solution Overview
Problem
Conventional approaches to protecting memory devices from row-hammer attacks are ineffective or inefficient, particularly when addressing non-adjacent neighboring rows, leading to potential data manipulation and security vulnerabilities.
Innovation Solution
Implementing a physically adjacent row mapping table to identify and refresh adjacent rows in volatile memory, using a non-volatile memory to store the mapping table and applying security protocols for access, thereby reducing computational complexity and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dummy reads are performed to neighboring rows by incrementing/decrementing addresses, then protection against row-hammer attacks is attempted, but addresses of non-adjacent rows are accessed resulting in incorrect refreshes and potential security vulnerabilities
Solution Approach 1:
The system pre-computes and stores the correct addresses of physically adjacent rows in a mapping table before any row-hammer attack occurs. When a row is accessed, the mapping table already contains the accurate neighboring row addresses, eliminating the need for real-time address calculation and ensuring precise identification of rows requiring refresh.
Solution Approach 2:
A mapping table is introduced as an intermediary data structure between the memory controller and the physical memory rows. This mapping table translates logical row addresses to their corresponding physically adjacent row addresses, acting as a mediator that ensures accurate identification of neighboring rows without directly manipulating memory addresses.
2Ease of manufacture
If address incrementing/decrementing is used to identify neighboring rows, then the implementation is simple, but it results in accessing non-adjacent rows and incorrect refreshes
Solution Approach 1:
The complex task of identifying physically adjacent row addresses is performed in advance and stored in a mapping table. This preliminary computation simplifies the runtime operation to a simple table lookup, maintaining implementation ease while ensuring refresh accuracy through pre-validated address mappings.
Solution Approach 2:
Instead of directly calculating neighboring row addresses through incrementing/decrementing operations, the system creates a copy of the address mapping relationship in a lookup table. This copied mapping information can be quickly retrieved without complex calculations, balancing simplicity with accuracy.
3Speed
If mapping tables are stored in volatile memory, then access speed is fast, but data persistence and security are compromised
Solution Approach 1:
The system transitions the mapping table from a single volatile memory location to a multi-dimensional storage architecture involving both non-volatile memory (for persistence and security) and volatile memory (for fast access). This dimensional change allows the mapping table to simultaneously achieve both speed and reliability requirements.
Solution Approach 2:
A cache mechanism acts as an intermediary between the non-volatile storage and the processing system. The mapping table is cached in volatile memory for fast access during runtime, while the original persistent copy remains secured in non-volatile memory, allowing both speed and persistence requirements to be satisfied simultaneously.
Data Source
AI summary
In some aspects, an apparatus includes a processing system that includes one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to send one or more memory access commands to a volatile memory. The one or more memory access commands are associated with a first address. The processing system if further configured to access, based on detecting a row-hammer condition associated with the one or more memory access commands, a physically adjacent row mapping table to determine at least a second address. The first address and the second address correspond to physically adjacent rows within the volatile memory. The processing system if further configured to send one or more row refresh commands to the volatile memory based on the row-hammer condition. The one or more row refresh commands are associated with at least the second address.