Physical Synthesis for Multi-Die IC Timing Convergence
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Solution Overview
Problem
Multi-die integrated circuits face challenges in achieving timing convergence and routability due to congestion and competition for limited inter-die wires, leading to unroutable circuit designs and increased runtime in electronic design automation (EDA) systems.
Innovation Solution
The implementation of physical synthesis techniques that analyze and modify candidate nets spanning multiple dies by relocating or replicating drivers and loads, performing incremental routing, and selectively committing changes based on timing analysis to reduce inter-die connections and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical synthesis is performed on candidate nets spanning multiple dies, then routing quality and timing convergence are improved, but device complexity and computational resources increase
Solution Approach 1:
The patent segments the circuit design into individual dies, with each die being processed and routed separately before final integration. This segmentation allows the routing algorithm to focus on local optimizations within each die rather than attempting to route all inter-die connections globally, thereby reducing computational complexity while maintaining routing quality.
Solution Approach 2:
The patent performs preliminary placement and routing of logic elements within each die before addressing inter-die connections. By pre-positioning drivers and loads and establishing intra-die routing first, the system reduces the complexity of subsequent inter-die net routing, as many routing decisions are already made and fixed.
2Object-generated harmful factors
If inter-die connections are reduced through physical synthesis, then congestion around die boundaries is reduced, but the number of processing steps increases
Solution Approach 1:
The patent changes the physical parameters of the circuit design by relocating drivers and loads to optimize net placement. By modifying the physical configuration of circuit elements within dies, the system reduces inter-die wire congestion without requiring additional processing steps beyond the physical synthesis operations.
3Reliability
If driver or load relocation is performed on candidate nets, then timing analysis improves and routability increases, but runtime of EDA system increases
Solution Approach 1:
The patent applies driver and load relocation selectively to specific candidate nets that span multiple dies and exhibit timing or routing issues, rather than uniformly processing all nets. This localized approach improves timing convergence for critical paths while minimizing the overall runtime impact on the EDA system.
4Manufacturing precision
If incremental routing is performed on modified candidate nets, then routing precision is improved, but computational resources and time increase
Solution Approach 1:
The patent applies incremental routing selectively to modified candidate nets that require improved routing precision, rather than performing exhaustive routing on all nets in the design. This partial action approach achieves necessary routing precision for critical inter-die connections while maintaining overall design flow speed.
Data Source
AI summary
Physical synthesis for a circuit design can include determining, using a processor, a candidate net from a circuit design, wherein the candidate net spans a plurality of dies of a multi-die integrated circuit, and modifying, using the processor, the candidate net by performing physical synthesis resulting in a modified candidate net. The physical synthesis includes relocating a driver or a load of the candidate net or replicating the driver of the candidate net. An incremental routing can be performed on the modified candidate net using the processor. Further, the modified candidate net can be selectively committed using the processor based upon a timing analysis.