Physical Synthesis for IC Timing Closure
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Solution Overview
Problem
Modern integrated circuit (IC) designs face challenges in meeting aggressive timing requirements due to the difficulty in determining which signal paths to optimize, and there is limited flexibility in changing the design after routing has been performed.
Innovation Solution
The implementation of physical synthesis optimizations within the placement process of IC design, allowing for modifications to the netlist before final component placement, including replicating, moving, or clustering drivers and loads across dies in multi-die ICs to improve timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing optimization is performed after routing, then timing requirements can be addressed, but flexibility for design changes is significantly reduced
Solution Approach 1:
The patent performs physical synthesis and timing optimization during the placement phase, which is before the routing phase. This preliminary action allows timing-critical signal paths to be identified and optimized early in the design flow, when components can still be moved and netlists can be modified. By conducting timing analysis and optimization before routing commits the design to fixed interconnect paths, the methodology maintains design flexibility while addressing timing requirements.
2Reliability
If physical synthesis is performed after placement, then final component locations are fixed, but timing optimization opportunities are lost
Solution Approach 1:
The patent performs physical synthesis during the placement phase rather than after placement is complete. This timing allows the synthesis tool to suggest component movements and netlist modifications while placement is still ongoing, capturing timing optimization opportunities that would be unavailable once placement is finalized. The methodology integrates physical synthesis into the placement workflow, enabling iterative optimization without requiring a separate post-placement synthesis pass.
Solution Approach 2:
The patent establishes a continuous feedback loop between placement and physical synthesis, where timing analysis results immediately inform placement adjustments. This continuous interaction allows timing optimization to proceed concurrently with placement rather than as a separate sequential step, reducing the overall time required for timing closure while maintaining both timing performance and placement quality.
3Ease of operation
If high-fanout reset nets are implemented, then circuit functionality is achieved, but timing closure becomes difficult
Solution Approach 1:
The patent applies physical synthesis to analyze high-fanout reset nets and identifies opportunities to segment them by inserting buffer components along the signal paths. This segmentation divides the large fanout net into smaller segments, each with reduced capacitive loading and shorter signal propagation distances. The buffer insertion strategy specifically targets reset nets with excessive fanout, improving timing closure while preserving the reset functionality across the entire circuit.
Solution Approach 2:
The patent introduces buffer components as intermediary elements between the reset source and the numerous flip-flop loads. These buffers act as mediators that drive segmented portions of the reset net, reducing the direct capacitive burden on the original reset source. By placing buffers at strategic locations identified through physical synthesis, the methodology reduces signal propagation delays and improves timing closure for high-fanout reset nets while maintaining their essential circuit functionality.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing physical synthesis with an overall placement process. One of the methods includes receiving an initial netlist of a circuit design for an IC. A global placement process is performed that assigns to some components in the initial netlist a respective initial location on the IC. One or more physical synthesis processes are performed to generate a modified netlist before assigning a final location to all components in the circuit design by an overall placement process. A subsequent placement process is performed to assign a final location on the IC to all components in the modified netlist.