Physically-tagged Data Cache Using Translation Context for Side Channel Mitigation
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Solution Overview
Problem
Side channel attacks exploit microarchitectural speculation in CPUs to leak sensitive information, such as encryption keys, by manipulating cache behavior and timing differences, which existing security measures fail to adequately mitigate.
Innovation Solution
Incorporating a translation context (TC) into the data cache memory allocation and access logic, ensuring that cache entries are only accessed by the same translation context that allocated them, thereby preventing attackers from exploiting cache hits for sensitive data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If speculative execution is enabled to improve CPU performance, then processing speed is improved, but security vulnerabilities increase due to side channel attacks
Solution Approach 1:
The patent segments the cache access logic by introducing translation context (TC) identification. Each cache entry is tagged with its originating TC, and cache accesses are segmented into different paths based on whether the accessing TC matches the tagged TC. This segmentation prevents cross-TC information leakage while preserving speculative execution within the same TC, thus maintaining performance while improving security.
Solution Approach 2:
The patent introduces translation context identification as an intermediary mechanism between the cache controller and cache entries. This intermediary verifies whether an accessing TC is authorized to access a particular cache entry, blocking unauthorized accesses that would otherwise leak sensitive information through side channels, while allowing legitimate speculative accesses to proceed.
2Productivity
If cache sharing is implemented to improve resource utilization, then hardware efficiency is improved, but information leakage between translation contexts increases
Solution Approach 1:
The patent applies local quality by making cache entry accessibility context-dependent. Instead of uniform cache sharing or isolation, each cache entry has its access permissions locally configured based on its TC tag. This allows fine-grained control where each entry can be selectively shared or isolated based on its security requirements, maintaining efficient resource utilization while preventing information leakage.
3Reliability
If cache access control is strengthened to improve security, then protection against side channel attacks is improved, but cache access performance deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-tagging each cache entry with its originating translation context during the cache allocation phase. This preliminary identification of TC ownership allows the cache controller to make rapid access decisions without complex runtime verification, as the TC match/mismatch can be determined through simple tag comparison, thus maintaining high access performance while ensuring security.
Data Source
AI summary
A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.