Pi-Coil Receiver Input for High-Speed Return and Insertion Loss
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Solution Overview
Problem
High-speed transceivers face challenges in mitigating return loss and insertion loss due to capacitive loads from ESD protection devices and on-die termination resistance, which degrade signal quality at higher data rates.
Innovation Solution
A pi-coil circuit is introduced, which contributes and hides capacitive loads by placing ESD and ODT capacitances at different mid-points of the pi-coil network, reducing input referred capacitance and improving insertion loss through AC peaking gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If t-coil networks are used to improve return loss and insertion loss, then signal quality is improved, but capacitive loads from ESD and ODT components still degrade performance at high data rates
Solution Approach 1:
The patent introduces an intermediary circuit configuration where the t-coil network is positioned between the capacitive loads (ESD and ODT components) and the receiver input. This intermediary structure transforms the harmful capacitive impedance into a more manageable form, allowing the receiver to operate effectively at high data rates despite the presence of these parasitic capacitances.
Solution Approach 2:
The patent modifies the electrical parameters of the receiver input stage by introducing the t-coil network, which changes the impedance characteristics and frequency response. This parameter transformation allows the system to compensate for the degradative effects of capacitive loads, improving return loss and insertion loss performance.
2Productivity
If data rate is increased to 25 Gbps or more to improve productivity, then transmission speed is improved, but signal bandwidth is impacted by capacitive loads
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the bandwidth-limiting effects of capacitive loads before the signal enters the receiver. The t-coil network is configured to provide anticipatory impedance transformation that counteracts the expected signal degradation, enabling the system to maintain effective bandwidth even at 25 Gbps and higher data rates.
3Reliability
If ESD and ODT components are added to protect against electrostatic discharge, then reliability is improved, but input referred capacitance increases
Solution Approach 1:
The patent converts the harmful effect of increased input referred capacitance into a beneficial outcome by using the t-coil network to transform this capacitance into an equivalent inductive effect at the receiver input. The ESD and ODT components, which originally increased capacitive load and degraded performance, are recontextualized as part of a compensated system where their capacitive effects are transformed into useful impedance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pi-coil circuit enhances input return loss and insertion loss by reducing capacitive impedance and increasing AC gain in specific frequency ranges, effectively addressing the limitations of t-coil networks.
Implementation Method 1
The pi-coil circuit comprises a first inductor coupled to a first mid-point of the pi-coil circuit, a second inductor coupled to a second mid-point of the pi-coil circuit, and a third inductor coupled in series between the first inductor and the second inductor
Data Source
AI summary
A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.