PI Flow Control for Lossless Shared Buffer Allocation

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Solution Overview

Problem

Current flow control mechanisms in data centers, such as IEEE 802.3x Pause and IEEE 802.1Qbb Priority Flow Control, fail to efficiently manage shared buffer space across input ports, leading to unfair buffer allocation and head-of-line blocking, where non-congested flows are affected by congested ones.

Innovation Solution

Implementing proportional integral (PI) flow control, where each source device's packet sending rate is individually determined based on its input packet count and a shared flow control threshold using PI controllers, ensuring fair buffer usage and preventing head-of-line blocking by smoothing packet sending rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If IEEE 802.3x Pause or IEEE 802.1Qbb Priority Flow Control is used to achieve lossless network, then packet drop is prevented, but buffer allocation becomes unfair and head-of-line blocking occurs

Engineering Contradiction:
Improvepacket loss preventionVSAvoidbuffer allocation fairness
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent divides the shared buffer into multiple virtual buffer queues, one for each input port or flow. This segmentation allows independent buffer management for each flow, preventing one flow from monopolizing the entire buffer and causing head-of-line blocking of other flows. Each flow gets guaranteed buffer space while maintaining overall buffer efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements differentiated buffer allocation where each input port or flow receives buffer space proportional to its traffic characteristics and congestion state. This local quality adjustment ensures that non-congested flows are not penalized by congested flows, achieving fair buffer allocation while maintaining lossless operation.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If a shared buffer is used at the switch, then buffer space is consolidated, but all senders are paused when the buffer is full even though not all are sending to congested ports

Engineering Contradiction:
Improvetotal buffer spaceVSAvoidsender throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The shared buffer is segmented into multiple virtual queues corresponding to different input ports or flows. This allows the buffer space to be dynamically allocated to active flows while isolating congested flows from affecting non-congested flows. The segmentation maintains total buffer utilization while preventing unfair pausing of senders.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic buffer allocation where buffer space is continuously adjusted based on real-time congestion feedback from each flow. When a flow becomes congested, its buffer allocation is reduced, and space is reallocated to non-congested flows. This dynamic adjustment ensures optimal buffer utilization while maintaining high sender throughput.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If one sender fills the whole buffer at the switch, then that sender gets maximum buffer space, but other senders are affected causing head-of-line blocking

Engineering Contradiction:
Improvebuffer occupancyVSAvoidflow independence
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the buffer into isolated virtual queues for each sender or flow, preventing any single sender from occupying the entire buffer. Each sender is limited to its allocated queue space, ensuring flow independence while maintaining overall buffer occupancy efficiency. This eliminates head-of-line blocking where one flow affects others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms that monitor buffer occupancy and congestion state for each flow. When a flow approaches its buffer allocation or detects congestion, the system adjusts packet transmission rates accordingly. This feedback ensures fair buffer distribution and prevents any single flow from dominating the buffer, maintaining both occupancy efficiency and flow independence.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10986026B2Proportional integral based shaper for lossless output buffer
Publication Date: 2021.04.20 CISCO TECHNOLOGY INC
  • US10986026B2 patent drawing
  • US10986026B2 patent drawing
  • US10986026B2 patent drawing

AI summary

A network device includes network ports to communicate with source devices and destination devices. The network device receives respective packets from each source device and, for each source device, respectively performs the following operations. The network device stores the respective packets in a shared memory that stores all packets from all of the source devices, and dequeues the respective packets from the shared memory to send the packets to destination devices. Responsive to the storing and the dequeuing, the network device respectively increases and decreases an input packet count for the source device. The network device determines for the source device a packet sending rate based on the input packet count and a flow control threshold common across all of the source devices in accordance with a proportional integral (PI) control equation. The network device transmits to the source device a control message including the packet sending rate.