PIC-EIC Copper Pillar Interconnects With Low Parasitic Offset
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Solution Overview
Problem
Conventional systems face limitations in connecting multiple chips with low latency and high speed for AI computing, leading to significant power consumption and excessive latency due to memory and interconnect bandwidth constraints.
Innovation Solution
A photonic interconnect platform featuring hybrid electro-photonic integrated circuits with modulators and photodetectors, allowing for efficient data routing using optical signals, and positioning components in close proximity to reduce thermal interference and electrical signal length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If components are positioned in close proximity to reduce electrical signal length, then signal transmission speed is improved, but thermal interference increases
Solution Approach 1:
The patent introduces thermal isolation structures as intermediary elements between the EIC and PIC components. These structures act as mediators that allow electrical signals to be transmitted through copper pillars while preventing thermal energy from the EIC from affecting the PIC components, thus resolving the contradiction between short signal paths and thermal interference
Solution Approach 2:
The patent segments the electrical interconnection system into distinct functional zones: electrical signal transmission paths (copper pillars) and thermal isolation paths (thermal isolation structures). This segmentation allows electrical signals to flow efficiently while thermal energy is blocked, enabling components to be in close proximity without thermal interference
2Quantity of substance
If data is transmitted using electrical signals between chips, then bandwidth is sufficient, but power consumption increases and latency increases
Solution Approach 1:
The patent replaces electrical signal transmission with optical signal transmission for data communication between chips. Optical signals carry data through photonic integrated circuits using light instead of electrical currents, achieving high bandwidth while consuming less power and reducing latency compared to conventional electrical interconnects
Solution Approach 2:
The hybrid electro-photonic integrated circuit package serves multiple functions: it performs electrical processing (EIC) and optical transmission (PIC) within a single unified package, enabling the system to leverage both electrical and optical domains for optimal performance in terms of bandwidth, power consumption, and latency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low latency, high bandwidth data transmission with reduced power consumption and interference, suitable for intra- and inter-chip routing in AI computing systems.
Implementation Method 1
The package encodes data from electrical signals into optical signals by modulating the optical signals using the modulators
Implementation Method 2
The package encodes data from optical signals into electrical signals using the photodetectors
Implementation Method 3
The PIC also includes waveguides for guiding optical signals to and from the modulators and to the photodetectors
Data Source
AI summary
A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.