3D PIC-EIC Layered Integration With Fiber-Aligned Output Ports
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Solution Overview
Problem
Forming connections between substrates in semiconductor devices poses challenges, particularly in integrating electronic integrated circuits (EICs) and photonic integrated circuits (PICs), which can lead to difficulties in thermal, physical, and electrical protection, as well as increased computational complexity.
Innovation Solution
A hybrid transceiver system is developed, comprising a support base with a photonic integrated circuit and an electronic integrated circuit, connected via a redistribution layer and a connecting element, with optical fibers and v-grooves for optical signal transmission, allowing for efficient integration and protection of both circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If connections are formed between substrates to integrate EICs and PICs, then computational power is increased, but thermal, physical, and electrical protection becomes difficult to provide
Solution Approach 1:
The system is divided into separate layers with distinct functions: a first layer for photonic integrated circuits and compute devices, a second layer for support and redistribution, and a third layer for additional compute devices. This segmentation allows each layer to be optimized independently for its specific function while providing collective protection and integration capabilities.
Solution Approach 2:
A redistribution layer is introduced as an intermediary between the photonic integrated circuit and the compute devices. This redistribution layer provides electrical connection and signal routing while also serving as a protective interface that manages thermal and electrical stresses between the different circuit components.
2Power
If multiple computational components are integrated into a single unit, then computational power is increased, but device complexity increases
Solution Approach 1:
The system transitions from planar integration to three-dimensional stacking, with multiple layers positioned at different vertical levels. The photonic integrated circuit and compute devices are arranged in separate layers connected via vertical redistribution layers, allowing high-density integration without increasing lateral footprint and simplifying the packaging approach.
3Speed
If optical fibers are coupled to photonic integrated circuits, then optical signal transmission is enabled, but alignment precision requirements increase
Solution Approach 1:
V-grooves are pre-formed in the photonic integrated circuit substrate during the manufacturing process. These grooves are designed with precise dimensions and orientations to receive and automatically align the optical fibers. The preliminary formation of these alignment features eliminates the need for post-assembly alignment adjustments, ensuring precise coupling between the optical fibers and the photonic circuit waveguides.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system enables effective thermal, electrical, and mechanical protection while enhancing computational power by facilitating efficient optical signal transmission and integration of EICs and PICs, thereby improving overall system performance.
Implementation Method 1
an optical fiber coupled to the optical coupler
Implementation Method 2
The output port may include one or more v-grooves extending in a direction parallel to the first layer
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Disclosed herein are systems, methods and device including a first layer with a photonic integrated circuit (104) and a first compute device (102), the photonic integrated circuit (104) having an output port (116) coupled to an optical fiber (114); the first layer may be positioned on a support base (101) in a second layer, while a connecting element (108) may couple the photonic integrated circuit (104) and the first compute device (102). The output port (116) may extend in a direction parallel with the first layer beyond the support base (101).