3D PIC-EIC Via Interconnects for Low-Voltage-Drop Packaging
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Solution Overview
Problem
Existing photonic computing systems face issues with excessive voltage drops due to long connection lines between electronic and photonic integrated circuit chips, leading to power consumption and limited integration due to numerous connection points and optical coupling challenges.
Innovation Solution
A semiconductor device with a photonic integrated circuit chip featuring a conductive structure in a via that electrically connects multiple electronic integrated circuit chips, reducing line distance and voltage drop through optimized wiring and optical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EIC chip and PIC chip are electrically connected with long connection lines, then electrical connection is achieved, but voltage drop increases and power consumption increases
Solution Approach 1:
The patent transitions from planar connection to three-dimensional stacking, placing EIC chips on both sides of the PIC chip and using vertical via structures to reduce connection path length. This dimensional change enables simultaneous achievement of reliable electrical connection and minimal voltage drop.
Solution Approach 2:
The patent embeds multiple EIC chips within a compact package structure around the PIC chip, with conductive vias nesting through the PIC chip substrate to establish electrical connections. This nested arrangement minimizes connection distance while maintaining reliable electrical connectivity.
2Productivity
If multiple connection points are used for data transmission, then data transmission capability is improved, but number of wiring lines increases and voltage drop increases
Solution Approach 1:
The patent utilizes vertical via structures to route multiple signal lines through the PIC chip substrate, enabling high-density interconnection in the vertical dimension. This reduces the horizontal wiring complexity while maintaining high data transmission capability through multiple connection points.
3Adaptability or versatility
If PIC chip has optical coupling with outside, then optical functionality is achieved, but integration is limited and package size increases
Solution Approach 1:
The patent combines optical coupling structures directly with the PIC chip substrate, integrating optical waveguides and coupling interfaces within the chip itself rather than as separate external components. This merging approach achieves optical functionality while maintaining compact integration.
Data Source
AI summary
The present invention relates to a field of photonic integrated circuits, which provides a semiconductor device. In some embodiments, the semiconductor device includes: a PIC chip including a conductive structure in a via; a first electronic integrated circuit chip (i.e., first EIC chip) arranged on a first surface of the PIC chip; a second electronic integrated circuit chip (i.e., second EIC chip) arrange on a second surface of the PIC chip; wherein the first EIC chip is electrically connected to the second EIC chip through the conductive structure in the via of the PIC chip. The semiconductor device of the present invention optimizes wiring of the PIC chip and can suppress a voltage drop caused by quite a long wire, optimizing a package structure.