Plasma Etched Trenches for PIC Thermal Management
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Solution Overview
Problem
Existing thermal management strategies for micro-ring resonators (MRRs) in photonic integrated circuits (PICs) are difficult to control, leading to unpredictable outcomes such as substantial undercut regions and the seepage of plating metal and molding material into openings, which complicates the bumping process and affects the reliability of thermal management.
Innovation Solution
A process involving plasma etching to create trenches on the PIC substrate without openings in the optical component strata, providing a controlled thermal management cavity that minimizes undercut regions and prevents the seepage of materials, allowing for enhanced thermal management and improved miniaturization of PICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing thermal management strategies are used to create thermal management cavities, then thermal management is provided for micro-ring resonators, but the process is difficult to control resulting in substantial undercut regions and material seepage
Solution Approach 1:
The patent replaces conventional wet etching processes with plasma etching to create thermal management cavities. Plasma etching provides superior anisotropy and control, eliminating the undercut regions and material seepage problems associated with wet etching while maintaining effective thermal management for micro-ring resonators
Solution Approach 2:
The patent changes the etching process parameters by using plasma-based etching instead of wet etching. This parameter change enables precise control of cavity depth and dimensions, preventing both insufficient thermal management and excessive undercutting, thereby achieving reliable thermal management with manufacturing precision
2Reliability
If openings are created in optical component strata to form thermal management cavities, then thermal management is achieved, but plating metal and molding material seep into the openings complicating the bumping process
Solution Approach 1:
The patent substitutes wet etching with plasma etching to form thermal management cavities. This substitution eliminates the need for openings in optical component strata, thereby preventing plating metal and molding material from seeping into the cavities and simplifying the subsequent bumping process while maintaining thermal management effectiveness
3Ease of manufacture
If conventional etching processes are used to create thermal management cavities, then cavities are formed, but undercut regions are created leading to unpredictable outcomes
Solution Approach 1:
The patent replaces conventional wet etching with plasma etching to form thermal management cavities. Plasma etching provides highly anisotropic etching with vertical sidewalls and precise depth control, eliminating the unpredictable undercut regions and dimension variations caused by wet etching while maintaining ease of cavity formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of thermal management cavities, reduces undercut regions, and prevents material seepage, resulting in improved thermal management and closer placement of optical components, enhancing the reliability and miniaturization of PICs.
Implementation Method 1
A process involving plasma etching to create trenches on the PIC substrate
Data Source
AI summary
A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.