Photonic Integrated Circuit Wafer Testing Surface Couplers
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Solution Overview
Problem
Photonic integrated circuits (PICs) face challenges in testing and evaluation due to the inaccessibility of facet couplers during wafer-level testing, which limits the ability to assess and characterize devices before dicing and packaging, leading to inefficiencies in identifying functional devices and increasing production costs.
Innovation Solution
Incorporating both facet and surface couplers as optical inputs or outputs on the same photonic integrated circuit, allowing for wafer-level testing through surface couplers while preserving the performance benefits of facet couplers during operation, such as low insertion loss and large optical bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If facet couplers are used for optical I/O, then low insertion loss and large optical bandwidth are achieved, but wafer-level testing becomes inaccessible
Solution Approach 1:
The optical I/O interface is segmented into two distinct types: facet couplers for low-loss operational coupling and surface couplers for wafer-level testing access. This segmentation allows each coupler type to fulfill its specific function without compromise, resolving the contradiction between operational performance and testing accessibility.
Solution Approach 2:
Surface couplers act as intermediary testing interfaces that enable wafer-level characterization without requiring facet coupler access. The surface couplers mediate between the testing equipment and the photonic circuit, allowing non-destructive testing while the facet couplers remain reserved for their optimal operational coupling function.
2Reliability
If only facet couplers are used, then optimal operational performance is achieved, but device characterization before dicing is impossible
Solution Approach 1:
Surface couplers are integrated into the device structure before dicing to enable preliminary wafer-level testing and characterization. This preliminary action allows functional verification and parameter measurement to be performed on the complete photonic circuit before the wafer is divided into individual devices, ensuring that only functional devices proceed to packaging.
Solution Approach 2:
The photonic integrated circuit is designed with multi-functionality: it can be tested and characterized at the wafer level through surface couplers, and then operated at the device level through facet couplers. This universal design allows the same circuit structure to serve both testing and operational purposes with different coupling interfaces.
3Ease of manufacture
If wafer-level testing is not performed, then production costs increase, but facet coupler inaccessibility is avoided
Solution Approach 1:
Surface couplers serve as intermediary testing ports that enable cost-effective wafer-level screening without compromising the operational integrity of the facet couplers. These surface couplers allow automated optical testing equipment to characterize devices on the wafer, enabling early identification of non-functional devices and reducing costly post-packaging failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates efficient wafer-level testing and characterization of PICs, enabling the identification of non-functional devices and reducing production costs by allowing testing before dicing, while ensuring optimal performance during normal operation using facet couplers post-dicing.
Implementation Method 1
A facet coupler couples to an external optical component via an edge of the substrate
Implementation Method 2
A surface coupler couples to an external optical component via a surface of the substrate
Data Source
AI summary
Techniques for forming a photonic integrated circuit having a facet coupler and a surface coupler are described. The photonic integrated circuit may be on a wafer, which may be diced to form an integrated device. The facet coupler may be positioned proximate to an edge of the integrated device, and the surface coupler may be positioned on a surface of the integrated device. The surface coupler may allow for evaluation and assessment of the circuit's performance, which may facilitate wafer-level testing of the circuit and diagnosis of the circuit before and after packaging.