Fork-Shaped Pick-Up Electrode Layout for Overlay-Tolerant Memory Cells
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Solution Overview
Problem
In the manufacturing of semiconductor memory devices, the overlay shift among masks in different layers leads to difficulties in achieving the target sizes for select gates and pick-up electrodes, resulting in reduced yield and reliability.
Innovation Solution
A pick-up structure for memory devices is designed with fork-shaped patterns and multi-layer resist structures to define pick-up electrodes, allowing for precise alignment and consistent widths, thereby improving overlap control and maintaining target sizes despite overlay shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used without improving overlay control, then manufacturing cost is reduced, but the width of pick-up electrodes cannot reach the target size
Solution Approach 1:
The patent applies preliminary action by defining the pick-up electrode pattern early in the manufacturing process, before the sacrificial material layer is removed. The fork-shaped pattern is formed in the first mask layer to define the main part and extension part of the pick-up electrode, ensuring the width reaches the target size before subsequent processing steps. This preliminary definition prevents overlay shifts from affecting the final electrode dimensions.
Solution Approach 2:
The patent segments the pick-up electrode into two distinct parts: a main part defined by fork-shaped patterns and an extension part that connects to the memory cell region. The fork-shaped pattern consists of multiple strips that define the main part, while the extension part has a reduced width. This segmentation allows different portions of the electrode to be optimized independently for their specific functions.
2Manufacturing precision
If high-resolution lithography process is adapted to improve overlap control, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent defines the pick-up electrode pattern in the first mask layer before removing the sacrificial material layer, ensuring that the electrode width reaches the target size. By performing this critical patterning step preliminarily, the invention achieves good overlap control using conventional lithography processes, avoiding the need for expensive high-resolution lithography while maintaining manufacturing precision.
3Ease of manufacture
If the pick-up electrode width does not reach the target size, then existing lithography processes can be used, but yield and reliability are reduced
Solution Approach 1:
The patent defines the pick-up electrode pattern in the first mask layer before removing the sacrificial material layer, ensuring that the electrode width reaches the target size. This preliminary definition ensures adequate electrode width for reliable contacts, improving yield and reliability while using existing lithography processes.
Solution Approach 2:
The patent implements local quality by giving different widths to different parts of the pick-up electrode. The main part has a larger width defined by the fork-shaped pattern to ensure adequate contact area and reliability, while the extension part has a reduced width optimized for its specific function of connecting to the memory cell region. This localized optimization ensures both reliability and manufacturability.
Data Source
AI summary
A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.


