PID Number Checking Circuit for Digital TV Decoder Conflict Resolution
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Solution Overview
Problem
In digital television decoders, the multiplexing of signal streams with shared PID numbers can lead to conflicts, and existing methods lack effective security measures for packet transmission.
Innovation Solution
A circuit that modifies PID numbers before further signal processing by checking if they fall within specific ranges and adjusting their values using a multiplexer, controller module, and adder system, with data stored in memory, allowing for conflict-free multiplexing and enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PID numbers are reused across different signal streams to increase channel capacity, then more services can be transmitted simultaneously, but PID number conflicts occur causing data packet mixing and processing errors
Solution Approach 1:
The PID number space is segmented into multiple ranges, with each range assigned to a specific signal stream or service type. The memory stores multiple PID ranges, and the system checks whether an incoming PID falls within any of these defined ranges to identify its source stream, thereby preventing confusion between streams that would occur with simple PID reuse.
Solution Approach 2:
An intermediary checking circuit is introduced between the demultiplexer and the signal processing stages. This circuit includes memory for storing PID ranges, an adder for calculating range boundaries, and control logic that mediates the PID validation process, determining whether each PID is valid and routing packets accordingly before they reach the main processing pipeline.
2Ease of manufacture
If a simple comparator-based PID filter is used to check PID numbers, then the implementation is straightforward, but it cannot effectively handle PID number conflicts from multiple signal streams
Solution Approach 1:
The system dynamically adapts to different PID ranges by loading appropriate range values into memory based on the active signal streams. The checking circuit can be reconfigured to recognize different PID ranges without hardware changes, allowing the same circuit to handle multiple service types and stream configurations flexibly.
Solution Approach 2:
The system changes the parameter space by not just comparing PIDs against fixed values, but against dynamically calculated ranges. The adder computes range boundaries by adding base values and offsets, allowing the checking logic to adapt to different PID allocation schemes by modifying the stored range parameters rather than changing the fundamental comparison mechanism.
3Reliability
If PID numbers are modified to prevent conflicts, then data packet accuracy is maintained, but additional circuit complexity is introduced for checking and modifying PIDs
Solution Approach 1:
The system performs preliminary checking of PID numbers against predefined ranges before packets are routed to processing stages. By validating PIDs early in the demultiplexing process and only modifying or rejecting them when necessary, the system avoids the need for complex real-time modification circuits for all packets, reducing overall complexity while maintaining reliability.
Solution Approach 2:
The system uses memory to store copies of PID range definitions and uses these stored values for comparison against incoming PIDs. This allows the complex range-checking logic to be implemented using simple memory lookups and comparisons, rather than requiring complex combinatorial logic circuits for each PID validation decision.
Data Source
AI summary
A device for checking numbers consists of a multiplexer (101) with a controller module (106) linked to it. An output of the multiplexer is connected to a first input of a register (102), which is an element of memory, while a first output of the controller module (106) is connected to an input of a storage (103) and a second input of the register (102). An output of the register (102) and an output of the storage (103) are connected to inputs of the adder (104), which adds on its output a number, stored in the register (102) and a number written in the storage (103) at an address indicated by the controller module (106). The adder (104) generates on its output a carry-out signal, informing about overflow, which is passed to a first controlling input of the controller module (106), which manages operation of the device checking numbers. A second controlling input of the controller module (106) is coupled a logical NOR type gate (105) passing a zero signal informing that the number on the output of the adder (104) equals zero.